[PATCH v2 5/6] arm64: dts: qcom: qcs615: enable pcie for qcs615 soc

[Bjorn Andersson]

On Fri, Nov 22, 2024 at 10:33:13AM +0800, Ziyue Zhang wrote:

The way we say "this is a DT patch for qcs615" is by prefixing the
subject "arm64: dts: qcom: qcs615: ", there's therefor no reason to
include "for qcs615" in the tail of the subject. You can further drop
the "soc" tail, as you said "qcs615" and not e.g. "qcs615-ride".

> Add configurations in devicetree for PCIe0, including registers, clocks,
> interrupts and phy setting sequence.
> 
> Signed-off-by: Krishna chaitanya chundru <quic_krichai at quicinc.com>

Patch has wrong Author.

> Signed-off-by: Ziyue Zhang <quic_ziyuzhan at quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 158 +++++++++++++++++++++++++++
>  1 file changed, 158 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 868808918fd2..c56cc30a59f3 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -678,6 +678,164 @@ rpmhpd_opp_turbo_l1: opp-9 {
>  		};
>  	};
>  
> +	pcie: pcie at 1c08000 {

This node looks to be in the wrong place.

Regards,
Bjorn

> +		compatible = "qcom,pcie-qcs615";
> +		reg = <0x0 0x01c08000 0x0 0x3000>,
> +		      <0x0 0x40000000 0x0 0xf1d>,
> +		      <0x0 0x40000f20 0x0 0xa8>,
> +		      <0x0 0x40001000 0x0 0x1000>,
> +		      <0x0 0x40100000 0x0 0x100000>,
> +		      <0x0 0x01c0b000 0x0 0x1000>;
> +
> +		reg-names = "parf",
> +			    "dbi",
> +			    "elbi",
> +			    "atu",
> +			    "config",
> +			    "mhi";
> +
> +		device_type = "pci";
> +		linux,pci-domain = <0>;
> +		bus-range = <0x00 0xff>;
> +		num-lanes = <1>;
> +
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +
> +		ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> +			 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +
> +		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "msi0",
> +				  "msi1",
> +				  "msi2",
> +				  "msi3",
> +				  "msi4",
> +				  "msi5",
> +				  "msi6",
> +				  "msi7",
> +				  "global";
> +
> +		interrupt-map = <0 0 0 0 &intc 0 0 0 140 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +
> +		interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS
> +				 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> +				<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> +				 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
> +		interconnect-names = "pcie-mem", "cpu-pcie";
> +
> +		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> +			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +			 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +			 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> +			 <&rpmhcc RPMH_CXO_CLK>;
> +
> +		clock-names = "aux",
> +			      "cfg",
> +			      "bus_master",
> +			      "bus_slave",
> +			      "slave_q2a",
> +			      "ref";
> +
> +		assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
> +		assigned-clock-rates = <19200000>;
> +
> +		operating-points-v2 = <&pcie_opp_table>;
> +
> +		resets = <&gcc GCC_PCIE_0_BCR>;
> +		reset-names = "pci";
> +
> +		phys = <&pcie_phy>;
> +		phy-names = "pciephy";
> +
> +		power-domains = <&gcc PCIE_0_GDSC>;
> +
> +		dma-coherent;
> +
> +		iommu-map = <0x0 &apps_smmu 0x400 0x1>,
> +			    <0x100 &apps_smmu 0x401 0x1>;
> +
> +		status = "disabled";
> +		pcie_opp_table: opp-table {
> +			compatible = "operating-points-v2";
> +
> +			/* GEN 1 x1 */
> +			opp-2500000 {
> +				opp-hz = /bits/ 64 <2500000>;
> +				required-opps = <&rpmhpd_opp_low_svs>;
> +				opp-peak-kBps = <250000 1>;
> +			};
> +
> +			/* GEN 2 x1 */
> +			opp-5000000 {
> +				opp-hz = /bits/ 64 <5000000>;
> +				required-opps = <&rpmhpd_opp_low_svs>;
> +				opp-peak-kBps = <500000 1>;
> +			};
> +
> +			/* GEN 3 x1 */
> +			opp-8000000 {
> +				opp-hz = /bits/ 64 <8000000>;
> +				required-opps = <&rpmhpd_opp_svs_l1>;
> +				opp-peak-kBps = <984500 1>;
> +			};
> +		};
> +
> +		pcie at 0 {
> +			device_type = "pci";
> +			reg = <0x0 0x0 0x0 0x0 0x0>;
> +			bus-range = <0x01 0xff>;
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			ranges;
> +		};
> +	};
> +
> +	pcie_phy: phy at 1c0e000 {
> +		compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
> +		reg = <0x0 0x01c0e000 0x0 0x1000>;
> +
> +		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> +			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			 <&gcc GCC_PCIE_0_CLKREF_CLK>,
> +			 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
> +			 <&gcc GCC_PCIE_0_PIPE_CLK>;
> +		clock-names = "aux",
> +			      "cfg_ahb",
> +			      "ref",
> +			      "refgen",
> +			      "pipe";
> +
> +		clock-output-names = "pcie_0_pipe_clk";
> +		#clock-cells = <0>;
> +
> +		#phy-cells = <0>;
> +
> +		resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> +		reset-names = "phy";
> +
> +		assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
> +		assigned-clock-rates = <100000000>;
> +
> +		status = "disabled";
> +	};
> +
>  	arch_timer: timer {
>  		compatible = "arm,armv8-timer";
>  		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> -- 
> 2.34.1
>