[PATCH v3 1/3] dt-bindings: phy: phy-imx8-pcie: Add header file for i.MX8Q HSIO SerDes PHY

[Richard Zhu]

Add lane index and HSIO configuration definitions of the i.MX8Q HSIO
SerDes PHY into header file.

Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
Reviewed-by: Frank Li <Frank.Li at nxp.com>
---
 include/dt-bindings/phy/phy-imx8-pcie.h | 62 +++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h
index 8bbe2d6538d8..60447b95a952 100644
--- a/include/dt-bindings/phy/phy-imx8-pcie.h
+++ b/include/dt-bindings/phy/phy-imx8-pcie.h
@@ -11,4 +11,66 @@
 #define IMX8_PCIE_REFCLK_PAD_INPUT	1
 #define IMX8_PCIE_REFCLK_PAD_OUTPUT	2
 
+/*
+ * i.MX8QM HSIO subsystem has three lane PHYs and three controllers:
+ * PCIEA(2 lanes capable PCIe controller), PCIEB (only support one
+ * lane) and SATA.
+ *
+ * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only
+ * support one lane) controller.
+ *
+ * In the different use cases. PCIEA can be bound to PHY lane0, lane1
+ * or Lane0 and lane1. PCIEB can be bound to lane1 or lane2 PHY. SATA
+ * can only be bound to last lane2 PHY.
+ *
+ * +-------------------------------+------------------+
+ * | i.MX8QM                       | i.MX8QXP         |
+ * |-------------------------------|------------------|
+ * |       | PCIEA | PCIEB | SATA  |       | PCIEB    |
+ * |-------------------------------|-------|----------|
+ * | LAN 0 | X     |       |       | LAN 0 | *        |
+ * |-------------------------------|-------|----------|
+ * | LAN 1 | X     | *     |       |       |          |
+ * |-------------------------------|-------|----------|
+ * | LAN 2 |       | *     | *     |       |          |
+ * +-------------------------------+------------------+
+ * NOTE:
+ * *: Choose one only.
+ * X: Choose any of these.
+ *
+ * Define i.MX8Q HSIO PHY lane index here to specify the lane mask.
+ */
+#define IMX8Q_HSIO_LANE0	0x1
+#define IMX8Q_HSIO_LANE1	0x2
+#define IMX8Q_HSIO_LANE2	0x4
+
+/*
+ * Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
+ * confiured as following three use cases.
+ *
+ * Define different configurations refer to the use cases, since it is
+ * mandatory required in the initialization.
+ *
+ * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY.
+ * Define "IMX8Q_HSIO_CFG_PCIEB" for i.MX8QXP platforms.
+ *
+ * +----------------------------------------------------+----------+
+ * |                               | i.MX8QM            | i.MX8QXP |
+ * |-------------------------------|--------------------|----------|
+ * |                               | LAN0 | LAN1 | LAN2 | LAN0     |
+ * |-------------------------------|------|------|------|----------|
+ * | IMX8Q_HSIO_CFG_PCIEAX2SATA    | PCIEA| PCIEA| SATA |          |
+ * |-------------------------------|------|------|------|----------|
+ * | IMX8Q_HSIO_CFG_PCIEAX2PCIEB   | PCIEA| PCIEA| PCIEB|          |
+ * |-------------------------------|------|------|------|----------|
+ * | IMX8Q_HSIO_CFG_PCIEAPCIEBSATA | PCIEA| PCIEB| SATA |          |
+ * |-------------------------------|------|------|------|----------|
+ * | IMX8Q_HSIO_CFG_PCIEB          | -    | -    | -    | PCIEB    |
+ * +----------------------------------------------------+----------+
+ */
+#define IMX8Q_HSIO_CFG_PCIEAX2SATA	0x1
+#define IMX8Q_HSIO_CFG_PCIEAX2PCIEB	0x2
+#define IMX8Q_HSIO_CFG_PCIEAPCIEBSATA	(IMX8Q_HSIO_CFG_PCIEAX2SATA | IMX8Q_HSIO_CFG_PCIEAX2PCIEB)
+#define IMX8Q_HSIO_CFG_PCIEB		IMX8Q_HSIO_CFG_PCIEAX2PCIEB
+
 #endif /* _DT_BINDINGS_IMX8_PCIE_H */
-- 
2.37.1