[PATCH 2/3] phy: zynqmp: Don't wait for PLL lock on nonzero PCIe lanes

Michal Simek michal.simek at amd.com
Mon Apr 22 23:25:45 PDT 2024



On 4/22/24 20:58, Sean Anderson wrote:
> Similarly to DisplayPort, nonzero PCIe lanes never achieve PLL lock [1].

What is this [1] for?

M



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