[PATCH v2 2/4] phy: qcom-qmp-pcie: add endpoint support for sa8775p

[Mrinmay Sarkar]

On 10/11/2023 5:06 PM, Dmitry Baryshkov wrote:
> On Wed, 11 Oct 2023 at 14:19, Mrinmay Sarkar <quic_msarkar at quicinc.com> wrote:
>> Add support for dual lane end point mode PHY found on sa8755p platform.
>>
>> Signed-off-by: Mrinmay Sarkar <quic_msarkar at quicinc.com>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c   | 41 ++++++++++++++++++++++++++++++
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h |  2 ++
>>   2 files changed, 43 insertions(+)
> Two minor questions.
>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> index a63ca74..962b4a1 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> @@ -2147,6 +2147,38 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[]
>>          QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
>>   };
>>
>> +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
> I should check whether we miss QSERDES_V5_COM_CMN_MODE in
> sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, which is otherwise nearly
> identical.
> Also do you need to set QSERDES_V5_COM_CORE_CLK_EN here?
QSERDES_V5_COM_CORE_CLK_EN is common for both RC and EP
so we are using it in sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl

-Mrinmay
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
>> +       QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl[] = {
>> +       QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
>> +};
> This is the same as sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl

so you want me to use sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl
instead of creating new one for sa8775?

-Mrinmay

>> +
>> +static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {
>> +       QMP_PHY_INIT_CFG(QPHY_V5_PCS_INSIG_MX_CTRL7, 0x00),
>> +       QMP_PHY_INIT_CFG(QPHY_V5_PCS_INSIG_SW_CTRL7, 0x00),
>> +};
> Could you please confirm that these registers belong to the V5
> namespace rather than V5_20 one?
may I know difference between V5 and V5_20 namespace
can't we use V5 namespace here?

-Mrinmay
>> +
>>   struct qmp_pcie_offsets {
>>          u16 serdes;
>>          u16 pcs;
>> @@ -3043,6 +3075,15 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
>>                  .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
>>          },
>>
>> +       .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
>> +               .serdes         = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,
>> +               .serdes_num     = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),
>> +               .pcs_misc       = sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl,
>> +               .pcs_misc_num   = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_ep_pcs_misc_tbl),
>> +               .pcs            = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,
>> +               .pcs_num        = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),
>> +       },
>> +
>>          .reset_list             = sdm845_pciephy_reset_l,
>>          .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
>>          .vreg_list              = qmp_phy_vreg_l,
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>> index 36cc80b..6ee1c33 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>> @@ -11,6 +11,8 @@
>>   #define QPHY_V5_PCS_PCS_STATUS1                                0x014
>>   #define QPHY_V5_PCS_POWER_DOWN_CONTROL                 0x040
>>   #define QPHY_V5_PCS_START_CONTROL                      0x044
>> +#define QPHY_V5_PCS_INSIG_SW_CTRL7                     0x060
>> +#define QPHY_V5_PCS_INSIG_MX_CTRL7                     0x07c
>>   #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1                        0x0c4
>>   #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2                        0x0c8
>>   #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3                        0x0cc
>> --
>> 2.7.4
>>
>