[PATCH v3 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes

[Varadarajan Narayanan]

On Wed, Mar 22, 2023 at 04:41:01PM +0200, Dmitry Baryshkov wrote:
> On Wed, 22 Mar 2023 at 12:46, Varadarajan Narayanan
> <quic_varada at quicinc.com> wrote:
> >
> > Add USB phy and controller related nodes
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada at quicinc.com>
> > ---
> >  Changes in v3:
> >         - Insert the nodes at proper location
> >
> >  Changes in v2:
> >         - Fixed issues flagged by Krzysztof
> >         - Fix issues reported by make dtbs_check
> >         - Remove NOC related clocks (to be added with proper
> >           interconnect support)
> > ---
> >  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 86 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 2bb4053..0943901 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -215,6 +215,48 @@
> >                 #size-cells = <1>;
> >                 ranges = <0 0 0 0xffffffff>;
> >
> > +               qusb_phy_0: phy at 7b000 {
> > +                       compatible = "qcom,ipq9574-qusb2-phy";
> > +                       reg = <0x07b000 0x180>;
>
> Please pad addresses to 8 hex digits.
>
>
> > +                       #phy-cells = <0>;
> > +
> > +                       clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > +                               <&xo_board_clk>;
> > +                       clock-names = "cfg_ahb", "ref";
> > +
> > +                       resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               ssphy_0: phy at 7d000 {
> > +                       compatible = "qcom,ipq9574-qmp-usb3-phy";
> > +                       reg = <0x7d000 0x1c4>;
> > +                       #clock-cells = <1>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       ranges;
> > +
> > +                       clocks = <&gcc GCC_USB0_AUX_CLK>,
> > +                                <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
>
> Could you please check the indentation here? Vertical lists should be aligned
>
> > +                       clock-names = "aux", "cfg_ahb";
>
> One item per line
>
> > +
> > +                       resets =  <&gcc GCC_USB0_PHY_BCR>,
> > +                                <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > +                       reset-names = "phy","common";
> > +                       status = "disabled";
> > +
> > +                       usb0_ssphy: phy at 7d200 {
>
> Newer bindings please, without subnodes.
>
> > +                               reg = <0x0007d200 0x130>,       /* tx */
> > +                                     <0x0007d400 0x200>,       /* rx */
> > +                                     <0x0007d800 0x1f8>,       /* pcs  */
> > +                                     <0x0007d600 0x044>;       /* pcs misc */
> > +                               #phy-cells = <0>;
> > +                               clocks = <&gcc GCC_USB0_PIPE_CLK>;
> > +                               clock-names = "pipe0";
> > +                               clock-output-names = "usb0_pipe_clk";
> > +                       };
> > +               };
> > +
> >                 pcie0_phy: phy at 84000 {
> >                         compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> >                         reg = <0x00084000 0x1bc>; /* Serdes PLL */
> > @@ -436,6 +478,50 @@
> >                         status = "disabled";
> >                 };
> >
> > +               usb3: usb3 at 8a00000 {
> > +                       compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> > +                       reg = <0x8af8800 0x400>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       ranges;
> > +
> > +                       clocks = <&gcc GCC_SNOC_USB_CLK>,
> > +                                <&gcc GCC_ANOC_USB_AXI_CLK>,
> > +                                <&gcc GCC_USB0_MASTER_CLK>,
> > +                                <&gcc GCC_USB0_SLEEP_CLK>,
> > +                                <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +
> > +                       clock-names = "sys_noc_axi",
> > +                                     "anoc_axi",
> > +                                     "master",
> > +                                     "sleep",
> > +                                     "mock_utmi";
> > +
> > +                       assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > +                                         <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +                       assigned-clock-rates = <200000000>,
> > +                                              <24000000>;
>
> Indentation?

Will address the above and post.

> > +
> > +                       resets = <&gcc GCC_USB_BCR>;
> > +                       status = "disabled";
> > +
> > +                       dwc_0: usb at 8a00000 {
> > +                               compatible = "snps,dwc3";
> > +                               reg = <0x8a00000 0xcd00>;
> > +                               clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +                               clock-names = "ref";
> > +                               interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > +                               phys = <&qusb_phy_0>, <&usb0_ssphy>;
> > +                               phy-names = "usb2-phy", "usb3-phy";
> > +                               tx-fifo-resize;
> > +                               snps,is-utmi-l1-suspend;
> > +                               snps,hird-threshold = /bits/ 8 <0x0>;
> > +                               snps,dis_u2_susphy_quirk;
> > +                               snps,dis_u3_susphy_quirk;
> > +                               dr_mode = "host";
>
> Is dr_mode a property of the host or of the board?

Board.

Thanks
Varada

> > +                       };
> > +               };
> > +
> >                 intc: interrupt-controller at b000000 {
> >                         compatible = "qcom,msm-qgic2";
> >                         reg = <0x0b000000 0x1000>,  /* GICD */
> > --
> > 2.7.4
> >
>
>
> --
> With best wishes
> Dmitry