[PATCH v2 05/13] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style of bindings

Konrad Dybcio konrad.dybcio at linaro.org
Mon Jul 31 12:22:33 PDT 2023


On 31.07.2023 12:57, Dmitry Baryshkov wrote:
> Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
> resource region, no per-PHY subnodes).
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 63 +++++++++++----------------
>  1 file changed, 26 insertions(+), 37 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 00ed71936b47..e4447a9d7929 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -211,59 +211,48 @@ qusb_phy_0: phy at 79000 {
>  
>  		pcie_qmp0: phy at 84000 {
>  			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
> -			reg = <0x00084000 0x1bc>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			ranges;
> +			reg = <0x00084000 0x1000>;
>  
>  			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
> -				<&gcc GCC_PCIE0_AHB_CLK>;
> -			clock-names = "aux", "cfg_ahb";
> +				<&gcc GCC_PCIE0_AHB_CLK>,
> +				<&gcc GCC_PCIE0_PIPE_CLK>;
Can you align the clocks entries?

Konrad



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