[PATCH v3 8/8] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs

[Abel Vesa]

On 23-01-18 06:34:41, Dmitry Baryshkov wrote:
> On 18/01/2023 02:53, Abel Vesa wrote:
> > Add the SM8550 both g4 and g3 configurations. In addition, there is a
> > new "lane shared" table that needs to be configured for g4, along with
> > the No-CSR list of resets.
> > 
> > Co-developed-by: Neil Armstrong <neil.armstrong at linaro.org>
> > Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
> > Signed-off-by: Abel Vesa <abel.vesa at linaro.org>
> > ---
> >   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 369 +++++++++++++++++++++++
> >   1 file changed, 369 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > index bffb9e138715..6f82604bd430 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > @@ -1506,6 +1506,234 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] =
> >   	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
> >   };
> 
> I see that the last two patches still use 'shrd' a lot. Does this correspond
> to hw register names or is it just a vendor kernel code convention?

It corresponds to the hw register names..

> 
> -- 
> With best wishes
> Dmitry
>