[PATCH 1/2] phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHY

[Dmitry Baryshkov]

The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the
PHY itself uses v5 regs. While there are only minor differences between
v4 and v5 regs and none of them concerns registers mentions in
regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove
possible confusion.

Fixes: bbe207a1aba1 ("phy: qcom-qmp-pcie: rename regs layout arrays")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 21727e90fad1..0e7aaff2ecfd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2164,7 +2164,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
 	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
 	.vreg_list		= qmp_phy_vreg_l,
 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
-	.regs			= pciephy_v4_regs_layout,
+	.regs			= pciephy_v5_regs_layout,
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
 	.phy_status		= PHYSTATUS,
-- 
2.39.0