[PATCH V2 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

[Roger Quadros]

Hi Sinthu,

On 06/01/2023 09:17, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja at ti.com>
> 
> The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
> for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
> USB PHY that is integrated into the SerDes IP. The WIZ control register
> has to be configured to support this lane swap feature.
> 
> The support for swapping lanes 2 and 3 is missing and therefore
> add support to configure the control register to swap between
> lanes 2 and 3 if PHY type is USB.
> 
> Signed-off-by: Sinthu Raja <sinthu.raja at ti.com>
> ---
> 
> Changes in V2:
> =============
> Address review comments:
> - Update commit description.
> - Rename enum variable name from wiz_lane_typec_swap_mode to wiz_typec_master_lane.
> - Rename enumerators name specific to list of master lanes used for lane swapping.
> - Add inline comments.
> 
> V1: https://lore.kernel.org/lkml/20221213124854.3779-2-sinthu.raja@ti.com/T/#m5e2d1a15d647f5df9dd28ed2dedc4b0812d6466f
> 
>  drivers/phy/ti/phy-j721e-wiz.c | 33 ++++++++++++++++++++++++++++++---
>  1 file changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> index 571f0ca18874..815e8124b94a 100644
> --- a/drivers/phy/ti/phy-j721e-wiz.c
> +++ b/drivers/phy/ti/phy-j721e-wiz.c
> @@ -58,6 +58,14 @@ enum wiz_lane_standard_mode {
>  	LANE_MODE_GEN4,
>  };
>  
> +/*
> + * List of master lanes used for lane swapping
> + */
> +enum wiz_typec_master_lane {
> +	LANE0 = 0,
> +	LANE2 = 2,
> +};
> +
>  enum wiz_refclk_mux_sel {
>  	PLL0_REFCLK,
>  	PLL1_REFCLK,
> @@ -194,6 +202,9 @@ static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
>  static const struct reg_field typec_ln10_swap =
>  					REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
>  
> +static const struct reg_field typec_ln23_swap =
> +					REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
> +
>  struct wiz_clk_mux {
>  	struct clk_hw		hw;
>  	struct regmap_field	*field;
> @@ -367,6 +378,7 @@ struct wiz {
>  	struct regmap_field	*mux_sel_field[WIZ_MUX_NUM_CLOCKS];
>  	struct regmap_field	*div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
>  	struct regmap_field	*typec_ln10_swap;
> +	struct regmap_field	*typec_ln23_swap;
>  	struct regmap_field	*sup_legacy_clk_override;
>  
>  	struct device		*dev;
> @@ -676,6 +688,13 @@ static int wiz_regfield_init(struct wiz *wiz)
>  		return PTR_ERR(wiz->typec_ln10_swap);
>  	}
>  
> +	wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
> +						       typec_ln23_swap);
> +	if (IS_ERR(wiz->typec_ln23_swap)) {
> +		dev_err(dev, "LN23_SWAP reg field init failed\n");
> +		return PTR_ERR(wiz->typec_ln23_swap);
> +	}
> +
>  	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
>  	if (IS_ERR(wiz->phy_en_refclk)) {
>  		dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
> @@ -1254,9 +1273,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
>  			int i;
>  

Don't you have to update the below comment you added in patch 1 to mention about LN23 as well?

+			/* if no typec-dir gpio was specified and PHY type is
+			 * USB3 with master lane number is '0', set LN10 SWAP
+			 * bit to '1'
+			 */


>  			for (i = 0; i < num_lanes; i++) {
> -				if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3)
> -						&& wiz->master_lane_num[i] == 0) {
> -					regmap_field_write(wiz->typec_ln10_swap, 1);
> +				if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
> +					switch (wiz->master_lane_num[i]) {
> +					case LANE0:
> +						regmap_field_write(wiz->typec_ln10_swap, 1);
> +						break;
> +					case LANE2:
> +						regmap_field_write(wiz->typec_ln23_swap, 1);
> +						break;
> +					default:
> +						break;
> +					}
>  				}
>  			}
>  		}

Otherwise looks good.

cheers,
-roger