[PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

[Roger Quadros]

On 20/02/2023 16:12, Swapnil Jakhade wrote:
> Add register sequences for PCIe + SGMII PHY multilink configuration.
> This has been validated on TI J7 platforms.
> 
> Signed-off-by: Swapnil Jakhade <sjakhade at cadence.com>

Reviewed-by: Roger Quadros <rogerq at kernel.org>