[PATCH 1/7] dt-bindings: PCI: qcom: Add IPQ9574 specific compatible
Devi Priya
quic_devipriy at quicinc.com
Mon Feb 20 05:29:31 PST 2023
Hi Krzysztof,
Thanks for taking time to review the patch!
On 2/16/2023 3:59 PM, Krzysztof Kozlowski wrote:
> On 14/02/2023 17:41, Devi Priya wrote:
>> Document the compatible for IPQ9574
>>
>> Signed-off-by: Devi Priya <quic_devipriy at quicinc.com>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 72 ++++++++++++++++++-
>> 1 file changed, 70 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index 872817d6d2bd..dabdf2684e2d 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -26,6 +26,7 @@ properties:
>> - qcom,pcie-ipq8064-v2
>> - qcom,pcie-ipq8074
>> - qcom,pcie-ipq8074-gen3
>> + - qcom,pcie-ipq9574
>> - qcom,pcie-msm8996
>> - qcom,pcie-qcs404
>> - qcom,pcie-sa8540p
>> @@ -44,11 +45,11 @@ properties:
>>
>> reg:
>> minItems: 4
>> - maxItems: 5
>> + maxItems: 6
>>
>> reg-names:
>> minItems: 4
>> - maxItems: 5
>> + maxItems: 6
>>
>> interrupts:
>> minItems: 1
>> @@ -105,6 +106,8 @@ properties:
>> items:
>> - const: pciephy
>>
>> + msi-parent: true
>> +
>> power-domains:
>> maxItems: 1
>>
>> @@ -173,6 +176,27 @@ allOf:
>> - const: parf # Qualcomm specific registers
>> - const: config # PCIe configuration space
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq9574
>> + then:
>> + properties:
>> + reg:
>> + minItems: 5
>> + maxItems: 6
>> + reg-names:
>> + minItems: 5
>> + items:
>> + - const: dbi # DesignWare PCIe registers
>> + - const: elbi # External local bus interface registers
>> + - const: atu # ATU address space
>> + - const: parf # Qualcomm specific registers
>> + - const: config # PCIe configuration space
>> + - const: aggr_noc #PCIe aggr_noc
>
> Why last one is optional? I would assume device either has it or has not.
>
Yes right, the device has aggr_noc.
The rate adapter update was required only for 1-lane PCIe
But will check and update this accordingly in the next spin.
>
> Best regards,
> Krzysztof
>
Best Regards,
Devi Priya
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