[PATCH 0/7] Add PCIe support for IPQ9574

[Devi Priya]

PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
are found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane
Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.

This series adds support for enabling the same

DTS patch is based on the crashdump series
https://lore.kernel.org/linux-arm-kernel/20230214051414.10740-1-quic_poovendh@quicinc.com/

Devi Priya (7):
  dt-bindings: PCI: qcom: Add IPQ9574 specific compatible
  PCI: qcom: Add IPQ9574 PCIe support
  dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 compatible
  phy: qcom-qmp-pcie: Add support for IPQ9574 platform
  dt-bindings: clock: Add PCIe pipe clock definitions
  clk: qcom: gcc-ipq9574: Add PCIe related clocks
  arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes

 .../devicetree/bindings/pci/qcom,pcie.yaml    |  72 ++-
 .../phy/qcom,ipq8074-qmp-pcie-phy.yaml        |  28 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts  |  28 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 477 +++++++++++++++++-
 drivers/clk/qcom/gcc-ipq9574.c                |  76 +++
 drivers/pci/controller/dwc/pcie-qcom.c        | 119 +++++
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 309 ++++++++++++
 .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h   |  26 +-
 .../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h   |   3 +
 include/dt-bindings/clock/qcom,ipq9574-gcc.h  | 276 +++++-----
 10 files changed, 1264 insertions(+), 150 deletions(-)


base-commit: 3ebb0ac55efaf1d0fb1b106f852c114e5021f7eb
-- 
2.17.1