[PATCH v4 1/6] phy: qcom-qmp-pcie: split register tables into common and extra parts
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Mon Sep 26 04:35:07 PDT 2022
On 26/09/2022 10:27, Johan Hovold wrote:
> On Sat, Sep 24, 2022 at 07:02:57PM +0300, Dmitry Baryshkov wrote:
>> SM8250 configuration tables are split into two parts: the common one and
>> the PHY-specific tables. Make this split more formal. Rather than having
>> a blind renamed copy of all QMP table fields, add separate struct
>> qmp_phy_cfg_tables and add two instances of this structure to the struct
>> qmp_phy_cfg. Later on this will be used to support different PHY modes
>> (RC vs EP).
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 ++++++++++++++---------
>> 1 file changed, 77 insertions(+), 52 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> index 7aff3f9940a5..30806816c8b0 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> @@ -1300,31 +1300,30 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
>> QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
>> };
>>
>> -/* struct qmp_phy_cfg - per-PHY initialization config */
>> -struct qmp_phy_cfg {
>> - int lanes;
>> -
>> - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
>> +struct qmp_phy_cfg_tables {
>> const struct qmp_phy_init_tbl *serdes_tbl;
>> int serdes_tbl_num;
>
> So I still think you should drop the now redundant "tbl" suffix and
> infix.
>
>> - const struct qmp_phy_init_tbl *serdes_tbl_sec;
>> - int serdes_tbl_num_sec;
>> const struct qmp_phy_init_tbl *tx_tbl;
>> int tx_tbl_num;
>> - const struct qmp_phy_init_tbl *tx_tbl_sec;
>> - int tx_tbl_num_sec;
>> const struct qmp_phy_init_tbl *rx_tbl;
>> int rx_tbl_num;
>> - const struct qmp_phy_init_tbl *rx_tbl_sec;
>> - int rx_tbl_num_sec;
>> const struct qmp_phy_init_tbl *pcs_tbl;
>> int pcs_tbl_num;
>> - const struct qmp_phy_init_tbl *pcs_tbl_sec;
>> - int pcs_tbl_num_sec;
>> const struct qmp_phy_init_tbl *pcs_misc_tbl;
>> int pcs_misc_tbl_num;
>> - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
>> - int pcs_misc_tbl_num_sec;
>> +};
>> +
>> +/* struct qmp_phy_cfg - per-PHY initialization config */
>> +struct qmp_phy_cfg {
>> + int lanes;
>> +
>> + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
>> + struct qmp_phy_cfg_tables common;
>
> And this could be "tbls_common".
I'd go for common_tables, if you don't mind.
>
>> + /*
>> + * Additional init sequence for PHY blocks, providing additional
>> + * register programming. Unless required it can be left omitted.
>> + */
>> + struct qmp_phy_cfg_tables *extra;
>
> And "tbls_extra".
>
> I guess this table should be const as well.
Ack
>
>>
>> /* clock ids to be requested */
>> const char * const *clk_list;
>> @@ -1459,6 +1458,7 @@ static const char * const sdm845_pciephy_reset_l[] = {
>> static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
>> .lanes = 1,
>>
>> + .common = {
>> .serdes_tbl = ipq8074_pcie_serdes_tbl,
>> .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
>> .tx_tbl = ipq8074_pcie_tx_tbl,
>> @@ -1467,6 +1467,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
>> .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
>> .pcs_tbl = ipq8074_pcie_pcs_tbl,
>> .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
>> + },
>
> Shouldn't you indent the members now? The above looks unnecessarily hard
> to read.
I wanted to keep the indentation to make the patch small enough, but
let's indent these lines (while dropping the _tbl from names as you
insisted).
>
>> .clk_list = ipq8074_pciephy_clk_l,
>> .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
>> .reset_list = ipq8074_pciephy_reset_l,
>
> @@ -1603,24 +1612,28 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
>> static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
>> .lanes = 1,
>>
>> + .common = {
>> .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
>> .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
>> - .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
>> - .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
>> .tx_tbl = sm8250_qmp_pcie_tx_tbl,
>> .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
>> .rx_tbl = sm8250_qmp_pcie_rx_tbl,
>> .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
>> - .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
>> - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
>> .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
>> .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
>> - .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
>> - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
>> .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
>> .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
>> - .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
>> - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
>> + },
>> + .extra = &(struct qmp_phy_cfg_tables) {
>
> const structure?
Ack
>
>> + .serdes_tbl = sm8250_qmp_gen3x1_pcie_serdes_tbl,
>> + .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
>> + .rx_tbl = sm8250_qmp_gen3x1_pcie_rx_tbl,
>> + .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
>> + .pcs_tbl = sm8250_qmp_gen3x1_pcie_pcs_tbl,
>> + .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
>> + .pcs_misc_tbl = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
>> + .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
>
> Indentation.
>
>> + },
>> .clk_list = sdm845_pciephy_clk_l,
>> .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
>> .reset_list = sdm845_pciephy_reset_l,
>
>> @@ -1854,11 +1881,9 @@ static int qmp_pcie_serdes_init(struct qmp_phy *qphy)
>> {
>> const struct qmp_phy_cfg *cfg = qphy->cfg;
>> void __iomem *serdes = qphy->serdes;
>> - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
>> - int serdes_tbl_num = cfg->serdes_tbl_num;
>>
>> - qmp_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
>> - qmp_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec);
>> + qmp_pcie_configure(serdes, cfg->regs, cfg->common.serdes_tbl, cfg->common.serdes_tbl_num);
>> + qmp_pcie_configure(serdes, cfg->regs, cfg->extra->serdes_tbl, cfg->extra->serdes_tbl_num);
>
> I already mentioned the NULL-derefs as cfg->extra can be NULL.
>
>>
>> return 0;
>> }
>
>> if (IS_ERR(qphy->pcs_misc)) {
>> - if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec)
>> + if (cfg->common.pcs_misc_tbl || cfg->extra->pcs_misc_tbl)
>
> Here too.
>
>> return PTR_ERR(qphy->pcs_misc);
>> }
>
> Johan
--
With best wishes
Dmitry
More information about the linux-phy
mailing list