[PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices

Dmitry Baryshkov dmitry.baryshkov at linaro.org
Fri Nov 18 14:22:10 PST 2022


On 16/11/2022 16:26, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 05:20:11PM +0300, Dmitry Baryshkov wrote:
>> On 10/11/2022 13:53, Johan Hovold wrote:
>>> On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote:
>>>> Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
>>>> platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
>>>>    1 file changed, 244 insertions(+), 2 deletions(-)
>>>
>>>> @@ -1761,6 +1957,52 @@ tlmm: pinctrl at f100000 {
>>>>    			gpio-ranges = <&tlmm 0 0 204>;
>>>>    			wakeup-parent = <&pdc>;
>>>>    
>>>> +			pcie0_default_state: pcie0-default-state {
>>>> +				perst-pins {
>>>> +					pins = "gpio94";
>>>> +					function = "gpio";
>>>> +					drive-strength = <2>;
>>>> +					bias-pull-down;
>>>> +				};
>>>> +
>>>> +				clkreq-pins {
>>>> +					pins = "gpio95";
>>>> +					function = "pcie0_clkreqn";
>>>> +					drive-strength = <2>;
>>>> +					bias-pull-up;
>>>> +				};
>>>> +
>>>> +				wake-pins {
>>>> +					pins = "gpio96";
>>>> +					function = "gpio";
>>>> +					drive-strength = <2>;
>>>> +					bias-pull-up;
>>>> +				};
>>>> +			};
>>>
>>> The pinconfig should go in the board file.
>>
>> Usually yes. However for the PCIe we usually put them into the main
>> .dtsi. See sm8[124]50.dtsi.
> 
> Yeah, I noticed that too and had this discussion with Bjorn for
> sc8280xp some months ago. Even if you may save a few lines by providing
> defaults in a dtsi, the pin configuration is board specific and belongs
> in the dts.

I see that you've ended up with no pin configuration at all in 
sc8280xp.dtsi. I must admit, this is an interesting approach. However I 
fear that this might increase c&p amount. Let's see how it goes in the 
long term.

> 
> Also note that 'perst' and 'wake' above could in principle be connected
> to other GPIOs on different boards.

Yes. Do we see that in wild? No.

-- 
With best wishes
Dmitry




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