[PATCH v4 10/16] dt-bindings: phy: qcom,qmp-pcie: rename current bindings
Vinod Koul
vkoul at kernel.org
Sat Nov 5 05:09:42 PDT 2022
On 29-10-22, 10:47, Johan Hovold wrote:
> On Fri, Oct 28, 2022 at 05:57:01PM -0400, Krzysztof Kozlowski wrote:
> > On 28/10/2022 09:35, Johan Hovold wrote:
> > > The current QMP PCIe PHY bindings are based on the original MSM8996
> > > binding which provided multiple PHYs per IP block and these in turn were
> > > described by child nodes.
> > >
> > > Later QMP PCIe PHY blocks only provide a single PHY and the remnant
> > > child node does not really reflect the hardware.
> > >
> > > The original MSM8996 binding also ended up describing the individual
> > > register blocks as belonging to either the wrapper node or the PHY child
> > > nodes.
> > >
> > > This is an unnecessary level of detail which has lead to problems when
> > > later IP blocks using different register layouts have been forced to fit
> > > the original mould rather than updating the binding. The bindings are
> > > arguable also incomplete as they only the describe register blocks used
> > > by the current Linux drivers (e.g. does not include the per lane PCS
> > > registers).
> > >
> > > In preparation for adding new bindings for SC8280XP which further
> > > bindings can be based on, rename the current schema file after IPQ8074,
> > > which was the first SoC added to the bindings after MSM8996 (which has
> > > already been split out), and add a reference to the SC8280XP bindings.
> > >
> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> > > Signed-off-by: Johan Hovold <johan+linaro at kernel.org>
> > > ---
> >
> > Also missing cc devicetree list.
>
> Yes, I know, but as I mentioned in my reply to Rob on the QMP USB
> series, I do not intend to repost this series unless someone insists as
> there were no binding-related changes in v4 (or v3).
It is always better to repost and get that out :-)
--
~Vinod
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