[PATCH v2 3/7] phy: sun4i-usb: Introduce port2 SIDDQ quirk

[Vinod Koul]

On 31-10-22, 11:13, Andre Przywara wrote:
> At least the Allwinner H616 SoC requires a weird quirk to make most
> USB PHYs work: Only port2 works out of the box, but all other ports
> need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
> RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
> the PMU PHY control register needs to be cleared. For this register to
> be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
> 
> Instead of disguising this as some generic feature, treat it more like
> a quirk (what it really is):
> If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
> this one special clock, and clear the SIDDQ bit. We also pick the clock
> and reset from PHY2 and enable them as well.

Applied, thanks

-- 
~Vinod