[PATCH v0.5 1/9] dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
Rob Herring
robh at kernel.org
Tue May 10 11:12:44 PDT 2022
On Fri, May 06, 2022 at 08:10:26PM +0200, Lucas Stach wrote:
> The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
> core with a little bit of SoC integration around it.
>
> Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> ---
> .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 73 +++++++++++++++++++
> 1 file changed, 73 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
> new file mode 100644
> index 000000000000..bd9a2b135176
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8MP DWC HDMI TX Encoder
> +
> +maintainers:
> + - Lucas Stach <l.stach at pengutronix.de>
> +
> +description: |
> + The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP.
> +
> +allOf:
> + - $ref: ../bridge/synopsys,dw-hdmi.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8mp-hdmi
> +
> + reg:
> + maxItems: 1
> +
> + reg-io-width:
> + const: 1
> +
> + clocks:
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - {}
> + - {}
> + - const: cec
> + - const: pix
> + - const: fdcc
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/imx8mp-clock.h>
> + #include <dt-bindings/power/imx8mp-power.h>
> +
> + hdmi at 32fd8000 {
> + compatible = "fsl,imx8mp-hdmi";
> + reg = <0x32fd8000 0x7eff>;
> + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_HDMI_APB>,
> + <&clk IMX8MP_CLK_HDMI_REF_266M>,
> + <&clk IMX8MP_CLK_32K>,
> + <&hdmi_tx_phy>;
> + clock-names = "iahb", "isfr", "cec", "pix";
The schema says there are 5 entries.
> + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
> + reg-io-width = <1>;
> + };
> --
> 2.30.2
>
>
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