[PATCH v2 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY

[AngeloGioacchino Del Regno]

Il 18/03/22 10:54, Jianjun Wang ha scritto:
> Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang at mediatek.com>
> ---
>   .../bindings/phy/mediatek,pcie-phy.yaml       | 75 +++++++++++++++++++
>   1 file changed, 75 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> new file mode 100644
> index 000000000000..868bf976568b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek PCIe PHY
> +
> +maintainers:
> +  - Jianjun Wang <jianjun.wang at mediatek.com>
> +
> +description: |
> +  The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8195-pcie-phy

Since I don't expect this driver to be only for MT8195, but to be extended to
support some more future MediaTek SoCs and, depending on the number of differences
in the possible future Gen4 PHYs, even different gen's, I propose to add a generic
compatible as const.

So you'll have something like:

- enum:
     - mediatek,mt8195-pcie-phy
- const: mediatek,pcie-gen3-phy

> +
> +  reg:
> +    maxItems: 1
> +

..snip..

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    phy at 11e80000 {
> +        compatible = "mediatek,mt8195-pcie-phy";

... which would reflect here as

compatible = "mediatek,mt8195-pcie-phy", "mediatek,pcie-gen3-phy"

> +        #phy-cells = <0>;
> +        reg = <0x11e80000 0x10000>;
> +        reg-names = "sif";
> +        nvmem-cells = <&pciephy_glb_intr>,
> +                      <&pciephy_tx_ln0_pmos>,
> +                      <&pciephy_tx_ln0_nmos>,
> +                      <&pciephy_rx_ln0>,
> +                      <&pciephy_tx_ln1_pmos>,
> +                      <&pciephy_tx_ln1_nmos>,
> +                      <&pciephy_rx_ln1>;
> +        nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
> +                           "tx_ln0_nmos", "rx_ln0",
> +                           "tx_ln1_pmos", "tx_ln1_nmos",
> +                           "rx_ln1";
> +        power-domains = <&spm 2>;
> +    };


Regards,
Angelo