[PATCH 3/3] phy: qcom-qmp: clean up hex defines

[Dmitry Baryshkov]

On 09/06/2022 15:03, Johan Hovold wrote:
> Use lower case hex consistently for define values.
> 
> Signed-off-by: Johan Hovold <johan+linaro at kernel.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>

> ---
>   drivers/phy/qualcomm/phy-qcom-qmp.h | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index 6d410826ae90..3a4f150dd499 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -30,7 +30,7 @@
>   #define QSERDES_PLL_CP_CTRL_MODE0			0x080
>   #define QSERDES_PLL_CP_CTRL_MODE1			0x084
>   #define QSERDES_PLL_PLL_RCTRL_MODE0			0x088
> -#define QSERDES_PLL_PLL_RCTRL_MODE1			0x08C
> +#define QSERDES_PLL_PLL_RCTRL_MODE1			0x08c
>   #define QSERDES_PLL_PLL_CCTRL_MODE0			0x090
>   #define QSERDES_PLL_PLL_CCTRL_MODE1			0x094
>   #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM			0x0a4
> @@ -44,7 +44,7 @@
>   #define QSERDES_PLL_DIV_FRAC_START3_MODE0		0x0e0
>   #define QSERDES_PLL_DIV_FRAC_START1_MODE1		0x0e4
>   #define QSERDES_PLL_DIV_FRAC_START2_MODE1		0x0e8
> -#define QSERDES_PLL_DIV_FRAC_START3_MODE1		0x0eC
> +#define QSERDES_PLL_DIV_FRAC_START3_MODE1		0x0ec
>   #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0		0x100
>   #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0		0x104
>   #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1		0x108
> @@ -270,11 +270,11 @@
>   #define QPHY_RX_MIN_HIBERN8_TIME			0x140
>   #define QPHY_RX_SIGDET_CTRL2				0x148
>   #define QPHY_RX_PWM_GEAR_BAND				0x154
> -#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB		0x1A8
> -#define QPHY_OSC_DTCT_ACTIONS				0x1AC
> -#define QPHY_RX_SIGDET_LVL				0x1D8
> -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB		0x1DC
> -#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB		0x1E0
> +#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB		0x1a8
> +#define QPHY_OSC_DTCT_ACTIONS				0x1ac
> +#define QPHY_RX_SIGDET_LVL				0x1d8
> +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB		0x1dc
> +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB		0x1e0
>   
>   /* Only for QMP V3 & V4 PHY - DP COM registers */
>   #define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
> @@ -639,7 +639,7 @@
>   #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xb8
>   #define QSERDES_V4_TX_TX_INTERFACE_MODE			0xbc
>   #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0xd8
> -#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdC
> +#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdc
>   #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0xe0
>   #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0xe4
>   #define QSERDES_V4_TX_VMODE_CTRL1			0xe8


-- 
With best wishes
Dmitry