[PATCH 2/2] phy: freescale: add Samsung HDMI PHY

[Lucas Stach]

Hi Krzysztof,

Am Sonntag, dem 28.08.2022 um 18:53 +0300 schrieb Krzysztof Kozlowski:
> On 26/08/2022 22:20, Lucas Stach wrote:
> > This adds the driver for the Samsung HDMI PHY found on the
> > i.MX8MP SoC. Based on downstream implementation from
> > Sandor Yu <Sandor.yu at nxp.com>.
> > 
> > Co-developed-by: Marco Felsch <m.felsch at pengutronix.de>
> > Signed-off-by: Marco Felsch <m.felsch at pengutronix.de>
> > Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> > ---
> >  drivers/phy/freescale/Kconfig                |   6 +
> >  drivers/phy/freescale/Makefile               |   1 +
> >  drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 699 +++++++++++++++++++
> >  3 files changed, 706 insertions(+)
> >  create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
> > 
> > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> > index 853958fb2c06..5c2b73042dfc 100644
> > --- a/drivers/phy/freescale/Kconfig
> > +++ b/drivers/phy/freescale/Kconfig
> > @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE
> >  	  Enable this to add support for the PCIE PHY as found on
> >  	  i.MX8M family of SOCs.
> >  
> > +config PHY_FSL_SAMSUNG_HDMI_PHY
> > +	tristate "Samsung HDMI PHY support"
> > +	depends on OF && HAS_IOMEM
> > +	help
> > +	  Enable this to add support for the Samsung HDMI PHY in i.MX8MP.
> 
> Your bindings do not mention that this IP block comes from Samsung, so
> please extend the description there.
> 
> Also, since this came from blocks used by Samsung, probably it shares a
> lot with Samsung Exynos SoC, so it would be nice to Cc maintainers of
> DRM DRIVERS FOR EXYNOS for some feedback.
> 
> Although existing Samsung HDMI phy driver is tightly coupled with Exynos
> DRM drivers, so not really re-usable without huge refactoring. I did not
> check the register layout similarities.
> 
I did take a look at the Exynos DRM HDMI driver, but this doesn't seem
to have much in common with what we do here. First the Exynos driver
mixes HDMI controller and PHY programming into a single driver, while
the PHY supported in this driver is paired to a Designware HDMI
controller on the i.MX8MP. Secondly the newest generation supported by
the Exynos driver is Exynos5 which is a 20nm part, while the i.MX8MP is
a 14nm part and PHYs tend to be really technology specific.

I'll CC the Exynos maintainers for the next submission, in case they
can provide some input, but I currently doubt that there is much
overlap.

Regards,
Lucas