[PATCH v6 resend 2/5] phy: Add LVDS configuration options

[Liu Ying]

On Wed, 2022-04-13 at 16:19 +0530, Vinod Koul wrote:
> On 13-04-22, 18:04, Liu Ying wrote:
> > Hi Vinod,
> > 
> > On Wed, 2022-04-13 at 11:41 +0530, Vinod Koul wrote:
> > > On 02-04-22, 13:24, Liu Ying wrote:
> > > > This patch allows LVDS PHYs to be configured through
> > > > the generic functions and through a custom structure
> > > > added to the generic union.
> > > > 
> > > > The parameters added here are based on common LVDS PHY
> > > > implementation practices.  The set of parameters
> > > > should cover all potential users.
> > > > 
> > > > Cc: Kishon Vijay Abraham I <kishon at ti.com>
> > > > Cc: Vinod Koul <vkoul at kernel.org>
> > > > Cc: NXP Linux Team <linux-imx at nxp.com>
> > > > Signed-off-by: Liu Ying <victor.liu at nxp.com>
> > > > ---

[...]

> > > > + */
> > > > +
> > > > +#ifndef __PHY_LVDS_H_
> > > > +#define __PHY_LVDS_H_
> > > > +
> > > > +/**
> > > > + * struct phy_configure_opts_lvds - LVDS configuration set
> > > > + * @bits_per_lane_and_dclk_cycle:	Number of bits per data
> > > > lane
> > > > and
> > > > + *					differential clock
> > > > cycle.
> > > 
> > > What does it mean by bits per data lane and differential clock
> > > cycle?
> > 
> > Please check
> > Documentation/devicetree/bindings/display/panel/lvds.yaml.
> > lvds.yaml metions slot.  'bits_per_lane_and_dclk_cycle' means the
> > number of slots.  But, I don't find the word 'slot' in my lvds
> > relevant
> > specs which mentioned in lvds.yaml, so 'slots' is probably not a
> > generic name(lvds.yaml is for display panel).  So, I use
> > 'bits_per_lane_and_dclk_cycle' as the name tells what it means.
> 
> variable name is fine, explanation for bit per lane and differential
> clock cycle didnt help, maybe add better explanation of what this
> variable means

I may add an example diagram as below...

> 
> > 
> > > 
> > > > + * @differential_clk_rate:		Clock rate, in Hertz,
> > > > of the
> > > > LVDS
> > > > + *					differential clock.
> > > > + * @lanes:				Number of active,
> > > > consecutive,
> > > > + *					data lanes, starting
> > > > from lane
> > > > 0,
> > > > + *					used for the
> > > > transmissions.
> > > > + * @is_slave:				Boolean, true if the
> > > > phy is a slave
> > > > + *					which works together
> > > > with a
> > > > master
> > > > + *					phy to support dual
> > > > link
> > > > transmission,
> > > > + *					otherwise a regular phy
> > > > or a
> > > > master phy.

---------------------------------8<------------------------------------
+ * This is an example with 4 lanes and 7 bits per data lane and
differential
+ * clock cycle:
+ *
+ * ::
+ *               |<------------- one differential clock cycle --------
----->|
+
*                ________________                         ____________
_____
+ *      Clock                     \_______________________/
+
*                  ______  ______  ______  ______  ______  ______  ____
__
+
*      Lane0     ><_bit0_><_bit1_><_bit2_><_bit3_><_bit4_><_bit5_><_bit
6_><
+
*      Lane1     ><_bit0_><_bit1_><_bit2_><_bit3_><_bit4_><_bit5_><_bit
6_><
+
*      Lane2     ><_bit0_><_bit1_><_bit2_><_bit3_><_bit4_><_bit5_><_bit
6_><
+
*      Lane3     ><_bit0_><_bit1_><_bit2_><_bit3_><_bit4_><_bit5_><_bit
6_><
---------------------------------8<------------------------------------

What do you think?

Regards,
Liu Ying