[PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements

[Greg KH]

On Fri, May 14, 2021 at 01:19:18PM +0200, Sergio Paracuellos wrote:
> On Fri, May 14, 2021 at 12:46 PM Vinod Koul <vkoul at kernel.org> wrote:
> >
> > On 08-05-21, 09:09, Sergio Paracuellos wrote:
> > > Hi all,
> > >
> > > This series contains some improvements in the pci phy driver
> > > for MT7621 SoCs.
> > >
> > > MT7621 SoC clock driver has already mainlined in
> > > 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> > >
> > > Because of this we can update schema documentation and device tree
> > > to add related clock entries and avoid custom architecture code
> > > in favour of using the clock kernel framework to retrieve clock
> > > frequency needed to properly configure the PCIe related Phys.
> > >
> > > After this changes there is no problem to properly enable this
> > > driver for COMPILE_TEST.
> > >
> > > Configuration has also modified from 'tristate' to 'bool' depending
> > > on PCI_MT7621 which seems to have more sense.
> >
> > Applied 2-6, thanks
> 
> Thanks, Vinod.
> 
> Greg, can you take patch 1 through your tree?

Sure, can you resend it?

thanks,

greg k-h