[PATCH 2/3] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver

[A, Rashmi]

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson at linaro.org>
> Sent: Friday, August 6, 2021 6:36 PM
> To: A, Rashmi <rashmi.a at intel.com>
> Cc: linux-drivers-review-request at eclists.intel.com; Michal Simek
> <michal.simek at xilinx.com>; linux-mmc <linux-mmc at vger.kernel.org>; Linux
> ARM <linux-arm-kernel at lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel at vger.kernel.org>; Kishon <kishon at ti.com>; Vinod Koul
> <vkoul at kernel.org>; Andy Shevchenko
> <andriy.shevchenko at linux.intel.com>; linux-phy at lists.infradead.org; Mark
> Gross <mgross at linux.intel.com>; kris.pan at linux.intel.com; Zhou, Furong
> <furong.zhou at intel.com>; Sangannavar, Mallikarjunappa
> <mallikarjunappa.sangannavar at intel.com>; Hunter, Adrian
> <adrian.hunter at intel.com>; Vaidya, Mahesh R
> <mahesh.r.vaidya at intel.com>; Srikandan, Nandhini
> <nandhini.srikandan at intel.com>; Demakkanavar, Kenchappa
> <kenchappa.demakkanavar at intel.com>
> Subject: Re: [PATCH 2/3] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC
> support to the arasan eMMC driver
> 
> On Fri, 30 Jul 2021 at 08:33, <rashmi.a at intel.com> wrote:
> >
> > From: Rashmi A <rashmi.a at intel.com>
> >
> > Intel Thunder Bay SoC eMMC controller is based on Arasan eMMC 5.1 host
> > controller IP
> >
> > Signed-off-by: Rashmi A <rashmi.a at intel.com>
> > Reviewed-by: Adrian Hunter <adrian.hunter at intel.com>
> 
> Rashmi, is it safe to apply this separately from the phy driver/dt changes?
> Then I can queue this via my mmc tree, if you like.
No, the phy driver/dt changes must go together with "mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver" patch.

Regards
Rashmi
> 
> Kind regards
> Uffe
> 
> > ---
> >  drivers/mmc/host/sdhci-of-arasan.c | 29
> ++++++++++++++++++++++++++++-
> >  1 file changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-arasan.c
> > b/drivers/mmc/host/sdhci-of-arasan.c
> > index 839965f7c717..6f202fb7a546 100644
> > --- a/drivers/mmc/host/sdhci-of-arasan.c
> > +++ b/drivers/mmc/host/sdhci-of-arasan.c
> > @@ -185,6 +185,13 @@ static const struct sdhci_arasan_soc_ctl_map
> intel_lgm_sdxc_soc_ctl_map = {
> >         .hiword_update = false,
> >  };
> >
> > +static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = {
> > +       .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
> > +       .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
> > +       .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
> > +       .hiword_update = false,
> > +};
> > +
> >  static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map
> = {
> >         .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
> >         .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, @@
> > -430,6 +437,15 @@ static const struct sdhci_pltfm_data
> sdhci_arasan_cqe_pdata = {
> >                         SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
> >  };
> >
> > +static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = {
> > +       .ops = &sdhci_arasan_cqe_ops,
> > +       .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
> > +       .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> > +               SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
> > +               SDHCI_QUIRK2_STOP_WITH_TC |
> > +               SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
> > +};
> > +
> >  #ifdef CONFIG_PM_SLEEP
> >  /**
> >   * sdhci_arasan_suspend - Suspend method for the driver @@ -1098,6
> > +1114,12 @@ static struct sdhci_arasan_of_data
> sdhci_arasan_generic_data = {
> >         .clk_ops = &arasan_clk_ops,
> >  };
> >
> > +static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data =
> {
> > +       .soc_ctl_map = &thunderbay_soc_ctl_map,
> > +       .pdata = &sdhci_arasan_thunderbay_pdata,
> > +       .clk_ops = &arasan_clk_ops,
> > +};
> > +
> >  static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
> >         .ops = &sdhci_arasan_cqe_ops,
> >         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | @@ -1231,6
> > +1253,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
> >                 .compatible = "intel,keembay-sdhci-5.1-sdio",
> >                 .data = &intel_keembay_sdio_data,
> >         },
> > +       {
> > +               .compatible = "intel,thunderbay-sdhci-5.1",
> > +               .data = &sdhci_arasan_thunderbay_data,
> > +       },
> >         /* Generic compatible below here */
> >         {
> >                 .compatible = "arasan,sdhci-8.9a", @@ -1582,7 +1608,8
> > @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> >
> >         if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
> >             of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
> > -           of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
> > +           of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") ||
> > +           of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1"))
> > + {
> >                 sdhci_arasan_update_clockmultiplier(host, 0x0);
> >                 sdhci_arasan_update_support64b(host, 0x0);
> >
> > --
> > 2.17.1
> >