[PATCH] yenta: irq-routing for TI bridges - take 2
Julia Elbert
jelbert at magma.com
Wed Feb 25 12:44:56 GMT 2004
Hello,
Just wanted to thank you for all the patch information. I have been
auditing this list for help with my project.
I am working on allocating resources to bridges behind the cardbus
controller. Currently, with the 2.6 kernel, I am using a 1225 TI
controller and am able to hack the register information in for my 2 dec
bridges, which then allows me to enable a memory/prefetch window for my
pci video card that sits in our box of pci slots. This card uses the
brooktree part. I can then successfully load the bttv.ko for this pci
card that sits behind my bridges.
Your work is aiding in my final solution to support our MAGMA Expansion
Products under Linux as we support it under Windows and Apple.
To Do: this is my task
3. Test on all laptops, we have every cb controller you have listed.
2. Get pci cards with i/o working, I am not able to hack a pci card that
uses i/o write a patch.
1. Write resource allocation code patch for bridges behind cardbus
bridges.
I took our code from Windows that we use to patch bridges and put in my
current linux configuration.
Here it is if you are interested. We also end up setting cacheline and
latency values to 0x10 and 0xf8 for performance reasons.
Thanks again,
--Julia
static patchTable patchUp[] = {
/* TI Bridge Chips */
VID DID Reg Value
{0x104c, 0xAC16, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC19, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC1B, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC1C, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC1D, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC1E, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC1F, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC40, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC41, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC42, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC50, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC51, 32, 0x80, 0x0, 0xc000, 0},
{0x104c, 0xAC52, 32, 0x80, 0x0, 0xc000, 0},
/* Richo Bridge Chips */
{0x1180, 0x0465, 16, 0x80, 0x0, 0x0001, -1},
{0x1180, 0x0466, 16, 0x80, 0x0, 0x0001, -1},
{0x1180, 0x0475, 16, 0x80, 0x0, 0x0001, -1},
{0x1180, 0x0476, 16, 0x80, 0x0, 0x0001, -1},
{0x1180, 0x0478, 16, 0x80, 0x0, 0x0001, -1},
/* Mobility Controlers */
{0x14f2, 0x0001, 8, 0x58, 0x0, 0x0005, -1},
{0x14f2, 0x0002, 8, 0x58, 0x0, 0x0005, -1},
// {0x14f2, 0x0120, 8, 0x58, 0x0, 0x0005, -1},
/* ENE Bridge Chips */
{0x1524, 0x1211, 8, 0xC9, 0x42, 0x0004, -1}, /* ???? */
{0x1524, 0x1211, 16, 0x80, 0x00, 0xC000, -1}, /* ???? */
{0x1524, 0x1225, 8, 0xC9, 0x42, 0x0004, -1}, /* ???? */
{0x1524, 0x1225, 16, 0x80, 0x00, 0xC000, -1}, /* ???? */
{0x1524, 0x1410, 8, 0xC9, 0x42, 0x0004, -1},
{0x1524, 0x1410, 16, 0x80, 0x00, 0xC000, -1},
{0x1524, 0x1420, 8, 0xC9, 0x42, 0x0004, -1}, /* ???? */
{0x1524, 0x1420, 16, 0x80, 0x00, 0xC000, -1}, /* ???? */
/* Intel BAM Chipsets */
{0x8086, 0x2448, 16, 0x50, 0x0, 0x0004, -1}, //jme 82801BAM
PCI-> Hub
{0x8086, 0x244e, 16, 0x50, 0x0, 0x0004, -1}, //jme 82801BA
PCI-> Hub
{0xFFFF, 0xFFFF},
// end of table...
0
// just in case...
};
/* Register definitions for TI PCI-to-CardBus bridges */
#define TI_SYSTEM_CONTROL 0x0080 /* 32 bit */
#define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
#define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
#define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
#define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
#define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
#define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
#define TI122X_IRQMUX 0x008c /* 32 bit */
#define TI_RETRY_STATUS 0x0090 /* 8 bit */
#define TI_CARD_CONTROL 0x0091 /* 8 bit */
#define TI_DEVICE_CONTROL 0x0092 /* 8 bit */
#define TI_BUFFER_CONTROL 0x0093 /* 8 bit */
#define TI_DMA_0 0x0094 /* 32
bit */
#define TI_DMA_1 0x0098 /* 32
bit */
/* Card Control Register */
#define TI_CCR_RIENB 0x80
#define TI_CCR_ZVENABLE 0x40
#define TI_CCR_PCI_IRQ_ENA 0x20
#define TI_CCR_PCI_IREQ 0x10
#define TI_CCR_PCI_CSC 0x08
#define TI_CCR_SPKROUTEN 0x02
#define TI_CCR_IFG 0x01
#define TI1220_CCR_PORT_SEL 0x20
#define TI122X_CCR_AUD2MUX 0x04
/* Device Control Register */
#define TI_DCR_5V_FORCE 0x40
#define TI_DCR_3V_FORCE 0x20
#define TI_DCR_IMODE_MASK 0x06
#define TI_DCR_IMODE_ISA 0x02
#define TI_DCR_IMODE_SERIAL 0x04
#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
/* Buffer Control Regiser */
#define TI_BCR_CB_READ_DEPTH 0x08
#define TI_BCR_CB_WRITE_DEPTH 0x04
#define TI_BCR_PCI_READ_DEPTH 0x02
#define TI_BCR_PCI_WRITE_DEPTH 0x01
/* Register definitions for Toshiba ToPIC95 controllers */
#define TOPIC_SOCKET_CONTROL 0x0090 /* 32 bit */
#define TOPIC_SCR_IRQSEL 0x00000001
#define TOPIC_SLOT_CONTROL 0x00a0 /* 8 bit */
#define TOPIC_SLOT_SLOTON 0x80
#define TOPIC_SLOT_SLOTEN 0x40
#define TOPIC_SLOT_ID_LOCK 0x20
#define TOPIC_SLOT_ID_WP 0x10
#define TOPIC_SLOT_PORT_MASK 0x0c
#define TOPIC_SLOT_PORT_SHIFT 2
#define TOPIC_SLOT_OFS_MASK 0x03
#define TOPIC_CARD_CONTROL 0x00a1 /* 8 bit */
#define TOPIC_CCR_INTB 0x20
#define TOPIC_CCR_INTA 0x10
#define TOPIC_CCR_CLOCK 0x0c
#define TOPIC_CCR_PCICLK 0x0c
#define TOPIC_CCR_PCICLK_2 0x08
#define TOPIC_CCR_CCLK 0x04
#define TOPIC97_INT_CONTROL 0x00a1 /* 8 bit */
#define TOPIC97_ICR_INTB 0x20
#define TOPIC97_ICR_INTA 0x10
#define TOPIC97_ICR_STSIRQNP 0x04
#define TOPIC97_ICR_IRQNP 0x02
#define TOPIC97_ICR_IRQSEL 0x01
#define TOPIC_CARD_DETECT 0x00a3 /* 8 bit */
#define TOPIC_CDR_MODE_PC32 0x80
#define TOPIC_CDR_VS1 0x04
#define TOPIC_CDR_VS2 0x02
#define TOPIC_CDR_SW_DETECT 0x01
#define TOPIC_REGISTER_CONTROL 0x00a4 /* 32 bit */
#define TOPIC_RCR_RESUME_RESET 0x80000000
#define TOPIC_RCR_REMOVE_RESET 0x40000000
#define TOPIC97_RCR_CLKRUN_ENA 0x20000000
#define TOPIC97_RCR_TESTMODE 0x10000000
#define TOPIC97_RCR_IOPLUP 0x08000000
#define TOPIC_RCR_BUFOFF_PWROFF 0x02000000
#define TOPIC_RCR_BUFOFF_SIGOFF 0x01000000
#define TOPIC97_RCR_CB_DEV_MASK 0x0000f800
#define TOPIC97_RCR_CB_DEV_SHIFT 11
#define TOPIC97_RCR_RI_DISABLE 0x00000004
#define TOPIC97_RCR_CAUDIO_OFF 0x00000002
#define TOPIC_RCR_CAUDIO_INVERT 0x00000001
#define DEC_CHIP_CONTROL 0x40
#define DEC_BRIDGE_ARB 0x42
/* PCI_COMMAND Bits */
#define PCI_CMD_IO 0x1 /* Enable
response in I/O space */
#define PCI_CMD_MEMORY 0x2 /* Enable response in
Memory space */
#define PCI_CMD_MASTER 0x4 /* Enable bus mastering
*/
#define PCI_CMD_SPECIAL 0x8 /* Enable response to
special cycles */
#define PCI_CMD_INVALIDATE 0x10 /* Use memory write and
invalidate */
#define PCI_CMD_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_CMD_PARITY 0x40 /* Enable parity checking */
#define PCI_CMD_WAIT 0x80 /* Enable address/data stepping
*/
#define PCI_CMD_SERR 0x100 /* Enable SERR */
#define PCI_CMD_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_STATUS_FAST_BACK 0x80 /* Capable of back-to-back
writes */
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