[Linux-parport] Parport signals stability with SiS chipset

[tdlt at cecm.usp.br]

	I have the same problem here. My two computers have SiS chipsets
	and the signals at pins are not set up correctly (at least not
	as I would like to see them).

	When I write data to ports using outb(), the pins change for a
	while and return to the initial state. In the initial state some
	pins are high and others are low. Using a latch and one control
	pin I could notice that the pulse is maintained by at least 1us.

	The voltage at control pins are stable. I could set it once and
	measure the desired voltage after a long time (not one year but
	lots os seconds).
	
	I should use my circuit and I programmed it in MS-DOS
	where this problem doesn't exist while using the same computers.

-- 
Thiago A. M. Delatorre