[PATCH 5/7] arm64: dts: apple: t6030: Add NVMe device nodes

[Janne Grunau]

Apple silicon SoCs have a built-in NVMe host controller. Using it
requires device nodes for its IOMMU (SART), its mailbox and the ANS
coprocessor implementing the NVMe host controller.

Signed-off-by: Janne Grunau <j at jannau.net>
---
 arch/arm64/boot/dts/apple/t6030.dtsi | 42 ++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t6030.dtsi b/arch/arm64/boot/dts/apple/t6030.dtsi
index 524e532830e2..85a16d03e22f 100644
--- a/arch/arm64/boot/dts/apple/t6030.dtsi
+++ b/arch/arm64/boot/dts/apple/t6030.dtsi
@@ -537,6 +537,48 @@ pinctrl_aop: pinctrl at 374824000 {
 
 			apple,npins = <54>;
 		};
+
+		ans_mbox: mbox at 389408000 {
+			compatible = "apple,t6030-asc-mailbox",
+				     "apple,asc-mailbox-v4";
+			reg = <0x3 0x89408000 0x0 0x4000>;
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 839 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 840 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 841 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 842 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "send-empty", "send-not-empty",
+					  "recv-empty", "recv-not-empty";
+
+			#mbox-cells = <0>;
+			power-domains = <&ps_ans>;
+		};
+
+		sart: sart at 38dc50000 {
+			compatible = "apple,t6030-sart", "apple,t6000-sart";
+			reg = <0x3 0x8dc50000 0x0 0xc000>;
+			power-domains = <&ps_ans>;
+		};
+
+		nvme: nvme at 38dcc0000 {
+			compatible = "apple,t6030-nvme-ans2",
+				     "apple,t8103-nvme-ans2";
+			reg = <0x3 0x8dcc0000 0x0 0x60000>,
+			      <0x3 0x89400000 0x0 0x4000>;
+			reg-names = "nvme", "ans";
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 851 IRQ_TYPE_LEVEL_HIGH>;
+
+			mboxes = <&ans_mbox>;
+
+			power-domains = <&ps_ans>, <&ps_apcie_sys_st>;
+			power-domain-names = "ans", "apcie0";
+			resets = <&ps_ans>;
+
+			apple,sart = <&sart>;
+		};
 	};
 
 	timer {

-- 
2.55.0