回复：[PATCH 1/3] nvme: Add adaptive PCIe link rate switching function

[Keith Busch]

On Thu, Nov 05, 2026 at 01:50:21PM +0800, 廖煊 wrote:
> However, L1 is entered only when the link is completely idle (no
> pending transactions). During active but low-utilization I/O, the link
> cannot enter L1 and typically stays trained at its maximum rate. This
> patch targets exactly that window: it dynamically downgrades the link
> rate to the minimum sufficient for the current traffic, and upgrades
> back to maximum when load rises.

ASPM operates on microsecond idle periods, so a lightly used link spends
most of its time detected as idle. Your threshold only selects the lower
rate below roughly 1.5MB/s on a Gen4 x4 link, which is essentially idle
where L1 would kick in more readily. Do you have shareable numbers that
show a real power benefit beyond ASPM?

> So the two mechanisms cover different link conditions and are
> complementary rather than conflicting: ASPM L1 handles the idle link,
> while this patch handles the active-but-underutilized link.

I don't think this kind of policy belongs in the kernel, much less in
the nvme driver. There are mechanisms for user space to control this,
though: the bwctrl cooling device lets user space set the link speed,
and diskstats provide utilization. A user space daemon can implement
this without kernel changes.

If you don't want to tie this to the PCIe thermal subsystem, maybe the
current_link_speed attribute could add a writeable callback instead?