[PATCH] nvme-pci: 512 byte aligned dma pool segment quirk

[Paweł Anikiel]

On Wed, Dec 11, 2024 at 11:56 AM Robert Beckett
<bob.beckett at collabora.com> wrote:
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>  ---- On Tue, 10 Dec 2024 21:36:55 +0000  Keith Busch  wrote ---
>  > On Mon, Dec 09, 2024 at 04:33:01PM +0100, Paweł Anikiel wrote:
>  > > On Mon, Dec 9, 2024 at 1:33 PM Robert Beckett bob.beckett at collabora.com> wrote:
>  > > > [...]
>  > > > I have no further updates on this. I have received no further info from the vendor.
>  > > > I think we can go ahead and use the alignment patch as is. The only outstanding question was whether it is an
>  > > > implicit last entry per page chain vs simple alisngment requirement. Either way, using the dmapool
>  > > > alignment fixes both of these potential causes, so we should just take it as is.
>  > > > If we ever get any better info and can do a more specific patch in future, we can rework it then.
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>  > > I think the 512 byte alignment fix is good. I tried coming up with
>  > > something more specific, but everything I could think of was either
>  > > too complicated or artificial.
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>  > > Regarding the question of whether this is an alignment requirement or
>  > > the last PRP entry issue, I strongly believe it's the latter. I have a
>  > > piece of code that clearly demonstrates the hardware bug when run on a
>  > > device with the nvme bridge. I would really appreciate it if this was
>  > > verified and my explanation was included in the patch.
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>  > I've pushed this to nvme-6.13 with an updated commit message here:
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>  >   https://git.infradead.org/?p=nvme.git;a=commitdiff;h=ccd84b8d6f4a60626dacb933b5d56dadca75c0ca
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> lgtm. Thanks!

Looks good to me as well. Thank you!