[PATCH] nvme: set controller enable bit in a separate write

[Christoph Hellwig]

This looks sensible.

On Thu, May 26, 2022 at 03:57:21PM +0200, Niklas Cassel wrote:
> @@ -2227,6 +2227,16 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
>  	ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
>  	ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
>  	ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
> +
> +	ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
> +	if (ret)
> +		return ret;
> +
> +	/* Flush write to device (required if transport is PCI) */
> +	ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
> +	if (ret)
> +		return ret;

Maybe we do eventually want a reg_write32_nonposted, but for now I
think this is sufficient.