PRP1 not min page size aligned in read/write cmds
Keith Busch
keith.busch at intel.com
Wed Apr 5 06:12:25 PDT 2017
On Tue, Apr 04, 2017 at 06:28:30PM -0700, Nisha Miller wrote:
> We have specified Min page size as 4K in our FW. So we expect that all
> read/write commands sent to FW will operate on multiples of 4K blocks.
> However we observe that sometimes we receive read/write commands where
> the PRP1 address is not 4K aligned, e.g 0x84CD5CD50. Is this normal or
> expected?
Yes, the first PRP entry and any list pointer may have an offset. The
remaining entries can not. See section 4.3, figure 14 in NVMe 1.2.1 spec.
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