automatic interrupt affinity for MSI/MSI-X capable devices V2
hch at lst.de
Thu Jun 16 08:22:37 PDT 2016
On Thu, Jun 16, 2016 at 11:45:55AM +0200, Bart Van Assche wrote:
> Is my interpretation correct that for an adapter that supports two
> interrupts and on a system with eight CPU cores and no hyperthreading this
> patch series will assign interrupt vector 0 to CPU 0 and interrupt vector 1
> to CPU 1?
Yes - same as the existing blk-mq queue distribution.
> Are you aware that drivers like ib_srp assume that interrupts
> have been spread evenly, that means assigning vector 0 to CPU 0 and vector
> 1 to CPU 4?
which will make them run into a conflict with the current blk-mq
assignment. That's exactly the point why we're trying to move things
to a core location so that everyone can use the same mapping.
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