>From 61e7c97a9035406a86442f7a05218d0938381b1c Mon Sep 17 00:00:00 2001
From: Alexander Dahl <ada@thorsis.com>
Date: Fri, 28 Jul 2017 14:30:49 +0200
Subject: [PATCH] dump nand and smc timings

---
 drivers/mtd/nand/atmel/nand-controller.c | 57 +++++++++++++++++++++++++++++++-
 1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c
index d922a88..f42ac8b 100644
--- a/drivers/mtd/nand/atmel/nand-controller.c
+++ b/drivers/mtd/nand/atmel/nand-controller.c
@@ -1413,9 +1413,64 @@ static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
 
 	nc = to_nand_controller(nand->base.controller);
 
+	dev_info(nc->dev, "atmel_smc_nand_setup_data_interface(csline: %i, type: %i)",
+		 csline, conf->type);
+	dev_info(nc->dev, "tBERS_max: %u, tCCS_min: %u, tPROG_max: %u, tR_max: %u",
+		 conf->timings.sdr.tBERS_max,
+		 conf->timings.sdr.tCCS_min,
+		 conf->timings.sdr.tPROG_max,
+		 conf->timings.sdr.tR_max);
+	dev_info(nc->dev, "tALH_min: %u, tADL_min: %u, tALS_min: %u, tAR_min: %u",
+		 conf->timings.sdr.tALH_min,
+		 conf->timings.sdr.tADL_min,
+		 conf->timings.sdr.tALS_min,
+		 conf->timings.sdr.tAR_min);
+	dev_info(nc->dev, "tCEA_max: %u, tCEH_min: %u, tCH_min: %u, tCHZ_max: %u",
+		 conf->timings.sdr.tCEA_max,
+		 conf->timings.sdr.tCEH_min,
+		 conf->timings.sdr.tCH_min,
+		 conf->timings.sdr.tCHZ_max);
+	dev_info(nc->dev, "tCLH_min: %u, tCLR_min: %u, tCLS_min: %u, tCOH_min: %u",
+		 conf->timings.sdr.tCLH_min,
+		 conf->timings.sdr.tCLR_min,
+		 conf->timings.sdr.tCLS_min,
+		 conf->timings.sdr.tCOH_min);
+	dev_info(nc->dev, "tCS_min: %u, tDH_min: %u, tDS_min: %u, tFEAT_max: %u",
+		 conf->timings.sdr.tCS_min,
+		 conf->timings.sdr.tDH_min,
+		 conf->timings.sdr.tDS_min,
+		 conf->timings.sdr.tFEAT_max);
+	dev_info(nc->dev, "tIR_min: %u, tITC_max: %u, tRC_min: %u, tREA_max: %u",
+		 conf->timings.sdr.tIR_min,
+		 conf->timings.sdr.tITC_max,
+		 conf->timings.sdr.tRC_min,
+		 conf->timings.sdr.tREA_max);
+	dev_info(nc->dev, "tREH_min: %u, tRHOH_min: %u, tRHW_min: %u, tRHZ_max: %u",
+		 conf->timings.sdr.tREH_min,
+		 conf->timings.sdr.tRHOH_min,
+		 conf->timings.sdr.tRHW_min,
+		 conf->timings.sdr.tRHZ_max);
+	dev_info(nc->dev, "tRLOH_min: %u, tRP_min: %u, tRR_min: %u, tRST_max: %llu",
+		 conf->timings.sdr.tRLOH_min,
+		 conf->timings.sdr.tRP_min,
+		 conf->timings.sdr.tRR_min,
+		 conf->timings.sdr.tRST_max);
+	dev_info(nc->dev, "tWB_max: %u, tWC_min: %u, tWH_min: %u, tWHR_min: %u",
+		 conf->timings.sdr.tWB_max,
+		 conf->timings.sdr.tWC_min,
+		 conf->timings.sdr.tWH_min,
+		 conf->timings.sdr.tWHR_min);
+	dev_info(nc->dev, "tWP_min: %u, tWW_min: %u",
+		 conf->timings.sdr.tWP_min,
+		 conf->timings.sdr.tWW_min);
+
 	ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
-	if (ret)
+	if (ret) {
+		dev_err(nc->dev, "atmel_smc_nand_prepare_smcconf() failed: %i", ret);
 		return ret;
+	}
+	dev_info(nc->dev, "smcconf: setup: 0x%08x, pulse: 0x%08x, cycle: 0x%08x, timings: 0x%08x, mode: 0x%08x",
+		 smcconf.setup, smcconf.pulse, smcconf.cycle, smcconf.timings, smcconf.mode);
 
 	if (csline == NAND_DATA_IFACE_CHECK_ONLY)
 		return 0;
-- 
2.1.4