>From 42584552cfe3055abebe4ac8a824fc5d527db9e2 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 6 May 2013 15:31:45 -0400 Subject: [PATCH 1/5] omap5: add qspi support Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter Signed-off-by: Sourav Poddar --- arch/arm/cpu/armv7/omap5/hw_data.c | 5 ++++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap5/omap.h | 3 +++ arch/arm/include/asm/arch-omap5/spl.h | 1 + arch/arm/include/asm/omap_common.h | 1 + 5 files changed, 10 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 716b931..c7a27e2 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -194,7 +194,7 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ - {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ + {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1} /* 20 MHz */ }; static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { @@ -488,6 +488,7 @@ void enable_basic_clocks(void) (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_qspi_clkctrl, 0 }; @@ -516,6 +517,8 @@ void enable_basic_clocks(void) clk_modules_explicit_en_essential, 1); + setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); + /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 426b50f..a7aa922 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -933,6 +933,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_l4per_gpio8_clkctrl = 0x4a009818, .cm_l4per_mmcsd3_clkctrl = 0x4a009820, .cm_l4per_mmcsd4_clkctrl = 0x4a009828, + .cm_l4per_qspi_clkctrl = 0x4a009838, .cm_l4per_uart1_clkctrl = 0x4a009840, .cm_l4per_uart2_clkctrl = 0x4a009848, .cm_l4per_uart3_clkctrl = 0x4a009850, diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 9ecc096..ab526ae 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -67,6 +67,9 @@ /* GPMC */ #define OMAP54XX_GPMC_BASE 0x50000000 +/* QSPI */ +#define QSPI_BASE 0x4B300000 + /* * Hardware Register Details */ diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index d4d353c..8905cb8 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -31,6 +31,7 @@ #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index a678bc0..55deacb 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -280,6 +280,7 @@ struct prcm_regs { u32 cm_l4per_mmcsd4_clkctrl; u32 cm_l4per_msprohg_clkctrl; u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_qspi_clkctrl; u32 cm_l4per_uart1_clkctrl; u32 cm_l4per_uart2_clkctrl; u32 cm_l4per_uart3_clkctrl; -- 1.7.1