--- mtd/drivers/mtd/nand/au1550nd.c	2005-10-31 18:37:29.000000000 +0100
+++ mtd-new/drivers/mtd/nand/au1550nd.c	2005-11-01 15:39:43.000000000 +0100
@@ -343,6 +343,16 @@ static void au1550_command(struct mtd_in
 	int ce_override = 0, i;
 	ulong flags;
 
+	/* Decide wether command needs to force-enable CE or not */
+	switch (command) {
+	case NAND_CMD_READ0:
+	case NAND_CMD_READ1:
+	case NAND_CMD_READOOB:
+	case NAND_CMD_READID:
+		ce_override = 1;
+		break;
+	}
+
 	/* Begin command latch cycle */
 	this->hwcontrol(mtd, NAND_CTL_SETCLE);
 	/*
@@ -382,9 +392,7 @@ static void au1550_command(struct mtd_in
 		if (page_addr != -1) {
 			this->write_byte(mtd, (u8)(page_addr & 0xff));
 
-			if (command == NAND_CMD_READ0 ||
-			    command == NAND_CMD_READ1 ||
-			    command == NAND_CMD_READOOB) {
+			if (ce_override) {
 				/*
 				 * NAND controller will release -CE after
 				 * the last address byte is written, so we'll
@@ -393,7 +401,6 @@ static void au1550_command(struct mtd_in
 				 * want the NOR flash or PCMCIA drivers to
 				 * steal our precious bytes of data...
 				 */
-				ce_override = 1;
 				local_irq_save(flags);
 				this->hwcontrol(mtd, NAND_CTL_SETNCE);
 			}
@@ -412,25 +419,7 @@ static void au1550_command(struct mtd_in
 	 * Program and erase have their own busy handlers.
 	 * Status and sequential in need no delay.
 	 */
-	switch (command) {
-
-	case NAND_CMD_PAGEPROG:
-	case NAND_CMD_ERASE1:
-	case NAND_CMD_ERASE2:
-	case NAND_CMD_SEQIN:
-	case NAND_CMD_STATUS:
-		return;
-
-	case NAND_CMD_RESET:
-		break;
-
-	case NAND_CMD_READ0:
-	case NAND_CMD_READ1:
-	case NAND_CMD_READOOB:
-		/* Check if we're really driving -CE low (just in case) */
-		if (unlikely(!ce_override))
-			break;
-
+	if (ce_override) {
 		/* Apply a short delay always to ensure that we do wait tWB. */
 		ndelay(100);
 		/* Wait for a chip to become ready... */
@@ -442,6 +431,19 @@ static void au1550_command(struct mtd_in
 		local_irq_restore(flags);
 		return;
 	}
+
+	switch (command) {
+
+	case NAND_CMD_PAGEPROG:
+	case NAND_CMD_ERASE1:
+	case NAND_CMD_ERASE2:
+	case NAND_CMD_SEQIN:
+	case NAND_CMD_STATUS:
+		return;
+		
+	case NAND_CMD_RESET:
+		break;
+	}
 	/* Apply this short delay always to ensure that we do wait tWB. */
 	ndelay(100);