[PATCH v2] mtd: spi-nor: clear the default RDCR opcode when entering Octal DTR

[haibo.chen at oss.nxp.com]

From: Haibo Chen <haibo.chen at nxp.com>

The core defaults opcodes.read_sr2 to the legacy RDCR opcode (0x35). In
8D-8D-8D mode the opcode is extended to two bytes per cmd_ext_type, but
the resulting command is not a valid SR2 read for these flashes, which
access their status/config registers through a vendor-specific indirect
register space. Since spi_nor_cache_sr_lock_bits() now reads SR2 during
init, i.e. after the switch to Octal DTR, the extended RDCR gets no data
back and the read times out (on i.MX FlexSPI: -ETIMEDOUT and a controller
WARN() during probe with Micron MT35xU and Macronix octal parts).

Clear read_sr2 when the switch to Octal DTR actually succeeds, so the SR2
read is skipped (a cleared opcode already means "unsupported"). Doing it
in spi_nor_set_octal_dtr() keys off the real runtime protocol: a flash
that advertises Octal DTR but runs in (x)STR because the host lacks
support keeps its usable RDCR.

Assisted-by: LLM
Fixes: b7b63475903c ("mtd: spi-nor: Create a local SR cache")
Fixes: 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support")
Signed-off-by: Haibo Chen <haibo.chen at nxp.com>
---
Changes in v2:
- Rework the fix following review: instead of guarding the read at runtime
  in spi_nor_read_sr2(), clear the default RDCR opcode.read_sr2 once, at the
  point the switch to Octal DTR succeeds (spi_nor_set_octal_dtr()).
- Key the clear off the real runtime protocol so a flash that advertises
  Octal DTR but runs in (x)STR (host without 8D support) keeps its RDCR.
- Drop the swp.c change and the -EOPNOTSUPP handling; a cleared read_sr2
  already means "no SR2 read", handled by the existing debugfs caching path.
- Trim the code comment; move the details to the commit message.
- Link to v1: https://lore.kernel.org/r/20260928-spi-nor-fix-v1-1-ce65ba90cfbd@nxp.com
---
 drivers/mtd/spi-nor/core.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 90524c58602e1c27cd83951ab0cdd3669a2ebfd6..5c0985491ade59cab317b74aab8572d7caedb64a 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3014,10 +3014,16 @@ static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
 	if (ret)
 		return ret;
 
-	if (enable)
+	if (enable) {
 		nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
-	else
+		/*
+		 * The default RDCR is not a valid SR2 read in Octal DTR mode;
+		 * clear it so SR2 reads are skipped instead of being issued.
+		 */
+		nor->params->opcodes.read_sr2 = 0;
+	} else {
 		nor->reg_proto = SNOR_PROTO_1_1_1;
+	}
 
 	return 0;
 }

---
base-commit: ba52b770f89bd2f3771b98edb92c4fde68ca8cc4
change-id: 20260928-spi-nor-fix-eb7ebe22a740

Best regards,
-- 
Haibo Chen <haibo.chen at nxp.com>