[RFC PATCH 2/4] spi: cadence-xspi: add ACMD support for SPI NAND

[Mark Brown]

On Wed, Sep 23, 2026 at 02:12:11PM +0800, Fei Xie wrote:

> The difficulty is that the hardware ACMD sequencer needs the complete
> multi-operation sequence to be described before it is started. For
> example, the SPI NAND core currently submits PAGE READ, status polling
> and READ CACHE as separate spi_mem_exec_op() calls. The STIG path can
> execute those operations individually, while the ACMD hardware combines
> them into one programmed sequence.

> Would an SPI-mem operation-sequence interface be a reasonable direction
> to explore? The NAND core could describe the ordered operations and
> polling condition, and the controller could either execute the sequence
> in hardware or fall back to the existing individual operations. This
> would keep NAND-specific knowledge out of the controller driver.

I think that makes sense, that mirrors some ideas people have had for
optimising SPI mesages in general - submit the sequence to the driver to
see if it can do it in one, falling back to just running individual
operations if that doesn't work.  See spi_optimize_message().
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