[PATCH v2] mtd: spi-nor: Fix quad-enable for flashes with QER bit in SR1

[Miquel Raynal]

Hello Michael,

On 11/09/2026 at 10:52:44 GMT, sashiko-bot at kernel.org wrote:

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] spi_nor_read_sr1_and_sr2() leaves sr[1] uninitialized when
> read_sr2 is unsupported, leading to uninitialized stack memory use in
> callers and spurious -EIO errors.

The annoyingly right Sashiko robot is correct :-)

The best way I see to make sure this does not appear, is to just add
this fallback to make sure when we read both registers we just get zero
instead of random data in the buffer. Again, the idea is to make sure
callers do not need to be "QER aware".

--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -867,6 +867,8 @@ int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr)
 
        if (nor->params->opcodes.read_sr2)
                ret = spi_nor_read_sr2(nor, &sr[1]);
+       else
+               sr[1] = 0;
 
        return ret;
 }

What do you think?

Thanks,
Miquèl