[RFC PATCH 0/4] spi: cadence-xspi: add ACMD PIO support for NAND and NOR

[Fei Xie]

Hi Nuno,

Thanks for proposing this. I agree that starting with your simpler ACMD
support makes sense. Please go ahead with that approach. I would be happy
to help test it on our Horizon J6B board.

To clarify my earlier benchmarks, "sequential read" referred to reading
consecutive addresses from /dev/mtd18 using dd, not the NAND device's
continuous-read mode. Our GD5F4GM8RE datasheet describes page-based reads
with cache output wrapping within the current page, and its SPI-NAND
driver entry does not advertise continuous-read support.

Could you point me to the version you would recommend testing? I can
compare it against the optimized STIG path and our combined NAND
read-sequence implementation under the same conditions, checking data
integrity, throughput and CPU usage.

That should help establish whether combining page-read, ready-poll and
read-cache operations provides enough additional benefit on this device
to justify further interface changes. We can then use those results to
decide what, if anything, should be built on top of the simpler ACMD
support.

I also agree that program and erase can remain on the STIG path, given
our results.

Thanks,
Fei