[PATCH v3 08/17] mtd: spi-nor: Fix WRSR with ODTR chips

[Miquel Raynal]

The ODTR interface requires an even number of bytes in each section of
the operation. spi_nor_spimem_setup_op() takes care of the opcode phase,
but we have to adapt the rest of the operation ourself.

Inspiration comes from the spi_nor_read_sr_ll() helper which faces a
similar case.

Make sure we don't face the sr1_and_sr2 case, which does not exist with
ODTR devices (this is a legacy behaviour on certain quad capable chips).

Fixes: 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support")
Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
---
 drivers/mtd/spi-nor/core.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index bc11c8cbb234..8e55f12161d1 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -778,7 +778,8 @@ static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
 {
 	int ret, i;
 
-	if (len > 2)
+	/* There is no sr1_and_sr2 in ODTR mode: this is a quad-only corner case */
+	if (len > 2  || (nor->reg_proto == SNOR_PROTO_8_8_8_DTR && len > 1))
 		return -EINVAL;
 
 	ret = spi_nor_write_enable(nor);
@@ -791,6 +792,14 @@ static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
 	if (nor->spimem) {
 		struct spi_mem_op op = SPI_NOR_WRSR_OP(opcode,
 						       nor->bouncebuf, len);
+		/*
+		 * We don't want to write only one byte in DTR mode, so
+		 * duplicate the buffer and write 2.
+		 */
+		if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+			op.data.nbytes = 2;
+			nor->bouncebuf[1] = nor->bouncebuf[0];
+		}
 
 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
 

-- 
2.55.0