[PATCH v2 5/5] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G

[Takahiro.Kuwano at infineon.com]

Hi,

> The MX66L1G45G supports the 1-4-4 DTR read mode. This flash uses 6
> dummy cycles by default in 1-4-4 DTR mode.
> 
> For 1S-4D-4D, its support bit is located in the 21st DWORD of the
> BFPT table, while the dummy cycles are described in the 23rd DWORD.
> Unfortunately, the BFPT of this flash model currently only supports
> 16 DWORDs, and the kernel's SFDP parser does not derive any
> SNOR_HWCAPS_READ_1_4_4_DTR capability from the BFPT table.
> 
> Therefore, implement late_init to initialize support for this opcode,
> configuring the read settings with the default 6 dummy cycles.
> 
Since the 1S-4D-4D support and dummy cycles are expected to be in BFPT,
this fix should be done in post_bfpt.

> The SFDP of this part provides a 4BAIT table, which also advertises
> the 4-byte 1-4-4 DTR opcode (0xEE). SFDP parsing converts the read
> opcodes to their 4-byte variants and spi_nor_set_4byte_opcodes() is
> skipped later on, but the 1-4-4 DTR read is only added in late_init,
> after 4BAIT has been parsed, so it is not converted there. Select
> the 4-byte opcode directly in that case.
> 
If 1S-4D-4D support is added in post_bfpt, conversion to 4-byte opcode
is done during 4BAIT table parse, right?

> Also set SPI_NOR_4B_OPCODES like MX66L51235F (0xc2 0x20 0x1a). The
> part supports the 4-byte opcode set, so if 4BAIT parsing does not
> complete, spi_nor_set_4byte_opcodes() still picks the 4-byte variants,
> including 0xEE for 1-4-4 DTR. With 4BAIT parsed, as on the tested
> part, the flag has no further effect.
> 
> Add a dedicated fixup for the part (SNOR_ID 0xc2, 0x20, 0x1b) that
> keeps the existing QPP 4-byte post-SFDP fixup and additionally
> advertises the 1-4-4 DTR read capability in late_init.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
> Reviewed-by: Miquel Raynal <miquel.raynal at bootlin.com>
> ---
> 

Thanks,
Takahiro