[PATCH v2] mtd: spi-nor: gigadevice: Add support for GigaDevice GD25B512

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] mtd: spi-nor: gigadevice: missing SPI_NOR_4BIT_BP on GD25B512
  entry
--

commit 80fcf8b510cb4dc992f3889cf33e42d0cc514639
Author: Matthew Parker <mparker at arista.com>

mtd: spi-nor: gigadevice: Add support for GigaDevice GD25B512

This commit adds a flash_info entry for the GigaDevice GD25B512 64 MiB SPI
NOR flash with Status Register locking enabled.

> diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
> index 6a2e6ebda1483..fe05c0f0370da 100644
> --- a/drivers/mtd/spi-nor/gigadevice.c
> +++ b/drivers/mtd/spi-nor/gigadevice.c
> @@ -64,6 +64,9 @@ static const struct flash_info gigadevice_nor_parts[] = {
>  		.id = SNOR_ID(0xc8, 0x40, 0x19),
>  		.name = "gd25q256",
>  		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
> +	}, {
> +		.id = SNOR_ID(0xc8, 0x47, 0x1a),
> +		.flags = SPI_NOR_HAS_LOCK,
>  	}, {
>  		.id = SNOR_ID(0xc8, 0x60, 0x16),
>  		.name = "gd25lq32",

[Severity: Medium]
Should this entry also set SPI_NOR_4BIT_BP in .flags?

The GD25B512 is a 64 MiB flash (1024 64 KiB blocks) that uses four Block
Protect bits (BP3:0 in Status Register 1 bits 5:2) to address its block
protection ranges.  Without SPI_NOR_4BIT_BP, spi_nor_get_sr_bp_mask()
omits SR_BP3, so spi_nor_sr_lock() and spi_nor_get_min_prot_length_sr()
miscalculate protected ranges by a factor of 16 (locking the full chip
only protects 4 MiB), and spi_nor_try_unlock_all() or spi_nor_sr_unlock()
cannot detect or clear SR_BP3 if it is set.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108024317.898917-1-mparker@arista.com?part=1