[PATCH v10 21/26] mtd: rawnand: sunxi: reset the H616 data path after DMA aborts
James Hilliard
james.hilliard1 at gmail.com
Thu Nov 5 10:55:37 PST 2026
Resetting an active H616 MDMA read with NFC_CTL.RESET can leave the first
1 KiB of the next read displaced. Both raw and ECC reads are affected,
including reads for which ECC reports success. Reissuing the NAND read
command and restoring the visible controller configuration do not correct
the internal data-path state. The DMA read error path can therefore return
incorrect data when it retries through PIO.
Pulse the controller's exclusive AHB reset after stopping an H616 DMA
operation. Drain interrupts before resetting the registers and clear the
pending events before accepting another command. The next operation
selects its chip and restores the page layout and timings; reads retry
from a fresh whole-page setup, while interrupted writes return an error.
Require the AHB reset at probe and exercise the same reset operation before
accepting transfers. Perform the AHB reset before releasing the DMA
mapping. This relies on the H616 CCU reset callback, which asserts
and deasserts the reset through register updates and returns success. The
reset handle pins the provider module, and the CCU driver suppresses sysfs
unbinding.
Propagate unexpected reset errors, leave the IRQ disabled and reject
subsequent commands. Avoid register access after failed recovery. Error
propagation is not a substitute for stopping DMA if the supported reset
provider contract is violated.
Select the stronger recovery through H616 capability data, leaving older
controllers' abort sequences unchanged.
Fixes: 5ee37db34637 ("mtd: rawnand: sunxi: add H616 MBUS DMA support")
Signed-off-by: James Hilliard <james.hilliard1 at gmail.com>
---
drivers/mtd/nand/raw/sunxi_nand.c | 90 +++++++++++++++++++++++++++++++++------
1 file changed, 76 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c
index e1306d14ab3a..e8286dc360ac 100644
--- a/drivers/mtd/nand/raw/sunxi_nand.c
+++ b/drivers/mtd/nand/raw/sunxi_nand.c
@@ -335,6 +335,7 @@ struct sunxi_nfc_mdma_desc {
* @has_ecc_block_512: If the ECC can handle 512B or only 1024B chunks
* @has_ecc_clk: If the controller needs an ECC clock.
* @has_mbus_clk: If the controller needs a mbus clock.
+ * @needs_bus_reset: Aborted DMA needs an AHB reset to restore data ordering
* @legacy_max_strength:If the maximize strength function was off by 2 bytes
* NB: this should not be used in new controllers
* @reg_io_data: I/O data register
@@ -368,6 +369,7 @@ struct sunxi_nfc_caps {
bool has_ecc_block_512;
bool has_ecc_clk;
bool has_mbus_clk;
+ bool needs_bus_reset;
bool legacy_max_strength;
unsigned int reg_io_data;
unsigned int reg_ecc_err_cnt;
@@ -412,6 +414,7 @@ struct sunxi_nfc_caps {
* @use_mdma: use an internal MBUS DMA backend
* @mdma_desc: H6-style MBUS DMA descriptor
* @mdma_desc_dma: DMA address of @mdma_desc
+ * @recovery_failed: reject further operations after unsuccessful recovery
* @caps: NAND Controller capabilities
*/
struct sunxi_nfc {
@@ -432,6 +435,7 @@ struct sunxi_nfc {
bool use_mdma;
struct sunxi_nfc_mdma_desc *mdma_desc;
dma_addr_t mdma_desc_dma;
+ bool recovery_failed;
const struct sunxi_nfc_caps *caps;
};
@@ -644,16 +648,50 @@ static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
struct scatterlist *sg)
{
dma_unmap_sg(nfc->dev, sg, 1, ddir);
+ /* Do not access controller registers after failed recovery. */
+ if (nfc->recovery_failed)
+ return;
+
writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
nfc->regs + NFC_REG_CTL);
}
-static void sunxi_nfc_dma_op_abort(struct sunxi_nfc *nfc)
+static int sunxi_nfc_dma_op_abort(struct sunxi_nfc *nfc)
{
- if (nfc->use_mdma)
- sunxi_nfc_rst(nfc);
- else
- dmaengine_terminate_all(nfc->dmac);
+ int ret;
+
+ if (!nfc->caps->needs_bus_reset) {
+ if (nfc->use_mdma)
+ sunxi_nfc_rst(nfc);
+ else
+ dmaengine_terminate_all(nfc->dmac);
+ return 0;
+ }
+
+ /* Drain the handler before resetting its registers. */
+ disable_irq(nfc->irq);
+ writel(0, nfc->regs + NFC_REG_INT);
+ readl(nfc->regs + NFC_REG_INT);
+
+ /* A soft reset alone can leave the first subsequent read displaced. */
+ sunxi_nfc_rst(nfc);
+ ret = reset_control_reset(nfc->reset);
+ if (ret)
+ goto failed;
+
+ writel(0, nfc->regs + NFC_REG_INT);
+ writel(NFC_INT_MASK, nfc->regs + NFC_REG_ST);
+ readl(nfc->regs + NFC_REG_INT);
+ enable_irq(nfc->irq);
+
+ /* The next operation selects the chip and restores its timing and layout. */
+ return 0;
+
+failed:
+ /* Keep the IRQ disabled and reject commands after failed recovery. */
+ nfc->recovery_failed = true;
+ dev_err(nfc->dev, "NAND controller recovery failed: %d\n", ret);
+ return ret;
}
static int sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
@@ -665,6 +703,9 @@ static int sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
u32 ctl;
int ret;
+ if (nfc->recovery_failed)
+ return -EIO;
+
if (cs >= sunxi_nand->nsels)
return -EINVAL;
@@ -1496,8 +1537,14 @@ static int sunxi_nfc_hw_ecc_read_batch_dma(struct nand_chip *nand,
nfc->regs + NFC_REG_CMD);
ret = sunxi_nfc_wait_events(nfc, wait, false, 0);
- if (ret)
- sunxi_nfc_dma_op_abort(nfc);
+ if (ret) {
+ int abort_ret = sunxi_nfc_dma_op_abort(nfc);
+
+ if (abort_ret) {
+ sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
+ return abort_ret;
+ }
+ }
sunxi_nfc_randomizer_disable(nand);
sunxi_nfc_hw_ecc_disable(nand);
@@ -1874,9 +1921,10 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
else
ret = nand_prog_page_begin_op(nand, page, 0, NULL, 0);
if (ret) {
- sunxi_nfc_dma_op_abort(nfc);
+ int abort_ret = sunxi_nfc_dma_op_abort(nfc);
+
sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
- return ret;
+ return abort_ret ?: ret;
}
/* exec_op() restores the page's spare base during column changes. */
@@ -1902,8 +1950,14 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
nfc->regs + NFC_REG_CMD);
ret = sunxi_nfc_wait_events(nfc, wait, false, 0);
- if (ret)
- sunxi_nfc_dma_op_abort(nfc);
+ if (ret) {
+ int abort_ret = sunxi_nfc_dma_op_abort(nfc);
+
+ if (abort_ret) {
+ sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
+ return abort_ret;
+ }
+ }
sunxi_nfc_randomizer_disable(nand);
sunxi_nfc_hw_ecc_disable(nand);
@@ -2904,11 +2958,18 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
}
}
- nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
+ if (nfc->caps->needs_bus_reset)
+ nfc->reset = devm_reset_control_get_exclusive(dev, "ahb");
+ else
+ nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
if (IS_ERR(nfc->reset))
- return PTR_ERR(nfc->reset);
+ return dev_err_probe(dev, PTR_ERR(nfc->reset), "failed to get AHB reset\n");
- ret = reset_control_deassert(nfc->reset);
+ /* Exercise the recovery reset operation before accepting DMA transfers. */
+ if (nfc->caps->needs_bus_reset)
+ ret = reset_control_reset(nfc->reset);
+ else
+ ret = reset_control_deassert(nfc->reset);
if (ret) {
dev_err(dev, "reset err %d\n", ret);
return ret;
@@ -3021,6 +3082,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_h616_caps = {
.has_mdma_desc = true,
.has_ecc_clk = true,
.has_mbus_clk = true,
+ .needs_bus_reset = true,
.reg_io_data = NFC_REG_A23_IO_DATA,
.reg_ecc_err_cnt = NFC_REG_H6_ECC_ERR_CNT,
.reg_user_data = NFC_REG_H6_USER_DATA,
--
2.53.0
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