[PATCH v5 03/28] mtd: spi-nor: Make sure the QE bit is kept enabled if useful

[Pratyush Yadav]

On Thu, May 07 2026, Miquel Raynal wrote:

> Not all chips implement the 4BAIT table which typically indicates the
> program capability, while many of them do implement the relevant SFDP
> parts indicating the read capabilities. In such a situation, programs
> can happen in single mode (1-1-1) and reads in quad mode (1-1-4 or
> 1-4-4). For the reads to work in such condition, the QE bit must be set.
> In case we later use the spi_nor_write_16bit_sr_and_check() helper with
> a chip with such configuration, the QE bit would get incorrectly
> cleared.
>
> Make sure this doesn't happen by keeping the QE bit under a simpler
> condition:
> - the quad enable hook is there (no change)
> - and at least one of the two protocols is based on quad I/O cycles
>
> Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>

Reviewed-by: Pratyush Yadav <pratyush at kernel.org>

-- 
Regards,
Pratyush Yadav