[PATCH v5 04/28] mtd: spi-nor: swp: Improve locking user experience

[Tudor Ambarus]

On 5/22/26 6:55 PM, Miquel Raynal wrote:
> On 22/05/2026 at 12:10:45 +03, Tudor Ambarus <tudor.ambarus at linaro.org> wrote:
> 
>> On 5/7/26 7:46 PM, Miquel Raynal wrote:
>>> Fixes: 3dd8012a8eeb ("mtd: spi-nor: add TB (Top/Bottom) protect support")
>>> Cc: stable at kernel.org
>> Fixes shall be the first patches in the set.
> 
> Technically speaking all four first patches are fixes, except I don't
> ask the first one to be backported. The reason why we ask fixes to be
> first in the series is because we want them to be as independent as
> possible from previous cleanups/changes. Here each four first patch are
> targeting completely different places and should not interact with each
> other. Anyway, I will re-shuffle the patches.

you don't need to resend just for that I think. Pratyush or Michael can
re-shuffle when applying.

> 
> As for Sashiko's feedback, the AI raises the same point as our previous
> discussion: the QE bit handling is really bad, and I am working on

I forgot what we talked about, sorry.

> improving this, in another series which waits for this one to land.
> 
> However the other warning it raises is IMO wrong: mixed-modes chips
> (either read or write working in quad mode, and the other in single

that's good to know, thanks. It assures people that the AI feedback was
considered.

> mode) should enable their QE bit anyway. Please raise a warning if you
> think this assumption is wrong.

Not sure if I'll be able to allocate time to review it. No blockers from
my side.

Cheers,
ta