[PATCH v4 10/27] mtd: spi-nor: swp: Create a helper that writes SR, CR and checks

[Miquel Raynal]

Hi Pratyush,

On 05/05/2026 at 18:05:11 +02, Pratyush Yadav <pratyush at kernel.org> wrote:

> On Fri, Apr 03 2026, Miquel Raynal wrote:
>
>> There are many helpers already to either read and/or write SR and/or CR,
>> as well as sometimes check the returned values. In order to be able to
>> switch from a 1 byte status register to a 2 bytes status register while
>> keeping the same level of verification, let's introduce a new helper
>> that writes them both (atomically) and then reads them back (separated)
>> to compare the values.
>>
>> In case 2 bytes registers are not supported, we still have the usual
>> fallback available in the helper being exported to the rest of the core.
>>
>> Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
>
> I'm confused. Doesn't spi_nor_write_16bit_sr_and_check() do the same
> thing? How are these two different?

The prototype says it all:

static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)

It writes sr1, and you can give only sr1. But because it is a 16bit
write, it also writes cr/sr2 on which the caller has no control. This
helper is actually very chip specific, because that is one way among the
different SFDP QER field possibilities to write the QE bit.

Giving more control to the caller, including the position of the QE bit
as well as the possibility to set other bits in cr/sr2 is what is
intended in this helper. This is an internal helper btw, only the core
uses it.

Note: I will send a v5 with an update of the naming convention because
it is not super satisfying. I already have that patch, and I was waiting
for this series to get in for sending the follow-up improvements, but if
we go for a new iteration I can include these patches in. There will be
a fix of the QE bit handling in the swp.c core I am touching as well (I
forgot to handle a case).

Thanks,
Miquèl