[PATCH 1/2] mtd: spi-nor: Fix RDCR controller capability core check

[Tudor Ambarus]

On 3/17/26 11:20 AM, Miquel Raynal wrote:
> Hello,
> 
>>>> These will always fail because there
>>>> is now an inconsistency: the address cycles are forced to 4 (then 3)
>>>> bytes, but the bus width during the address cycles rightfully remains 0:
>>>> impossible, the operation is invalid.
>>
>> I like Cheng's details on how it's failing. Would you please add what he
>> detailed there?
>> ```
>> This modified operation is then rejected by spi_mem_check_op() in the
>> core spi-mem.c because it has a non-zero address length but a zero address
>> buswidth, which is an invalid combination.
>> ```
> 
> I've added the precision about the invalid combination of non-zero
> address length and zero bus width. I feel like it's a repetition of my

oh, yes, I missed that.

> previous sentence, but I'm fine with it if it clarifies.

I'm fine either way. Thanks!