[PATCH v4 09/16] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383)

[Santhosh Kumar K]

Hello Miquel,

Apologies for the delayed response.

On 02/07/26 19:05, Miquel Raynal wrote:
> On 18/06/2026 at 13:07:18 +0530, Santhosh Kumar K <s-k6 at ti.com> wrote:
> 
>> Erratum i2383 on AM654 locks the address phase in PHY DDR mode when a
>> 2-byte column address is used. DDR PHY tuning must not be attempted for
>> such operations; non-PHY DDR usage is unaffected. [0]
>>
>> Add CQSPI_NO_2BYTE_ADDR_PHY_DDR quirk and check it in
>> cqspi_am654_ospi_execute_tuning(). When the erratum applies, return 0
>> with read_op->max_freq cleared.
>>
>> [0] https://www.ti.com/lit/er/sprz544c/sprz544c.pdf
>>
>> Signed-off-by: Santhosh Kumar K <s-k6 at ti.com>
>> ---
>>   drivers/spi/spi-cadence-quadspi.c | 17 ++++++++++++++++-
>>   1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
>> index 72768292a32b..22df5f3bdb96 100644
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -49,6 +49,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_DEVICE_CS_CNT_MAX);
>>   #define CQSPI_DISABLE_RUNTIME_PM	BIT(10)
>>   #define CQSPI_NO_INDIRECT_MODE		BIT(11)
>>   #define CQSPI_HAS_WR_PROTECT		BIT(12)
>> +#define CQSPI_NO_2BYTE_ADDR_PHY_DDR	BIT(13)
> 
> Can we rename the flag to make it more readable? I would propose:
> 
> #define CQSPI_NO_PHY_TUNING_WITH_ODDR_2B_ADDR	BIT(13)
> 
> Long, but more self explanatory.

Yeah, it is lengthy but I agree on your self-explanatory point. I'll
have it renamed in v5.

Thanks,
Santhosh.

> 
> Thanks,
> Miquèl