[PATCH v2 1/2] mtd: rawnand: pl353: Fix software ECC support

[Miquel Raynal]

Hello Andrea,

On 26/01/2026 at 17:58:55 +01, Andrea Scian via B4 Relay <devnull+andrea.scian.dave.eu at kernel.org> wrote:

> From: Andrea Scian <andrea.scian at dave.eu>
>
> We need to set another couple of fields in ecc structure to allow
> choosing SW ECC instead of HW one, otherwise write operation fail.

I'm not sure I captured in our previous exchanges that you were testing
with SW ECC.

> Signed-off-by: Andrea Scian <andrea.scian at dave.eu>
> ---
>  drivers/mtd/nand/raw/pl35x-nand-controller.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c
> index 11bd90e3f18cb..fcb62b9ec947b 100644
> --- a/drivers/mtd/nand/raw/pl35x-nand-controller.c
> +++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c
> @@ -976,6 +976,8 @@ static int pl35x_nand_attach_chip(struct nand_chip *chip)
>  		fallthrough;
>  	case NAND_ECC_ENGINE_TYPE_NONE:
>  	case NAND_ECC_ENGINE_TYPE_SOFT:
> +		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;

This is unfortunately not relevant here. In software you can use
whatever algorithm you want. It is writeable in DT and should not be
hardcoded here. The only limit is the available OOB area for the
strength (depending on the NAND geometry).

> +		chip->ecc.write_page_raw = nand_monolithic_write_page_raw;

This, however, seems relevant and should be the oneliner!

Please add Cc: stable & Fixes tags to your v3.

Thanks,
Miquèl