[RFC PATCH v2 00/12] spi: cadence-quadspi: add PHY tuning support

[Santhosh Kumar K]

On 05/02/26 21:18, Miquel Raynal wrote:
> Hi Santhosh,
> 
>> I am surprised by these numbers, I would expect these to get higher for
>> SPI NANDs. I will test the series and report my observations, especially
>> since there is also ODDR SPI NAND support now (in nand/next, should be
>> part of my upcoming merge request to Linus for 6.19+1);
> 
> I just tested the series, here are some numbers I grabbed on TI AM62A7
> LP SK with a Winbond W35N02 SPI NAND chip (so in the end very close to
> your report):
> 
>   +-----------------+-----------+------------+
>   | SPI NAND        | no tuning | PHY tuning |
>   | Unit: MiB/s     |   25MHz   |   166MHz   |
>   |-----------------+-----------+------------|
>   | Octal SDR read  |   13.8    |    34.2    |
>   |           write |    7.2    |    10.2    |
>   |-----------------+-----------+------------|
>   | Octal DTR read  |   21.2    |     N/A    |
>   |           write |    9.0    |     N/A    |
>   +-----------------+-----------+------------+
> 
> Please mind I used MiB/s and not MB/s (so kiB / 1024), I don't know
> which one you used for measuring, as you marked MB, whereas the most
> common unit seems to be MiB.
> 
> However PHY tuning failed in Octal DTR mode (your series applied on top
> of nand/next) with the following logs, can you have a look?
> 
> [    2.261647] spi-nand spi0.0: Winbond SPI NAND was found.
> [    2.266956] spi-nand spi0.0: 128 MiB, block size: 256 KiB, page size: 4096, OOB size: 128
> [    2.285257] cadence-qspi fc40000.spi: PHY tuning failed: -2
> [    2.290835] spi-nand spi0.0: Failed to execute PHY tuning: -2

Unfortunately, due to a known erratum in the Cadence controller, PHY DDR
mode cannot be used with 2-byte addressing.

Refer:
Errata i2383: OSPI: 2-byte address is not supported in PHY DDR mode [1]

As a result, the Cadence controller supports only the following
operating modes:
  - PHY DDR mode with 4-byte addressing
  - PHY SDR mode
  - TAP (non-PHY) DDR mode
  - TAP (non-PHY) SDR mode

[1] 
https://www.ti.com/lit/er/sprz544c/sprz544c.pdf?ts=1770404630843&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards,
Santhosh.

> 
> The fallback worked well though, the memory was still usable like
> before, which is a very good point.
> 
> Thanks,
> Miquèl