[PATCH 0/4] spi: spi-mem/mtd: spinand: Prevent SPI NAND continuous reads on am65/am62

[Miquel Raynal]

On 26/03/2026 at 17:47:14 +01, Miquel Raynal <miquel.raynal at bootlin.com> wrote:

> TI errata i2351 explains there is a problem with CS handling, SPI NOR
> are immune to the problem, but the CS being deasserted spuriously when
> there is DMA arbitration on long accesses (every 1023 bytes), SPI NAND
> continuous reads cannot be leveraged.
>
> Link: https://www.ti.com/lit/er/sprz544c/sprz544c.pdf
>
> I created a 2-page read setup for testing all variants available on a
> W35N chip wired to this controller. I reliably observed all variants to
> always (in my tests) report correct data, except the 8D-8D-8D
> variant *when setting an extended number of dummy cycles* (>= 12, so 24
> dummy bytes). In this case, I got the first 6144 bytes correct (over
> 8192), the rest being full of ones (0xFF), indicating the CS has likely
> been deasserted there. This is not exactly 6 x 1023 bytes (?), but
> close.
>
> This series shall be applied on top of the SPI NAND continuous read
> series that I am also carrying, but ideally not too far in the future
> because there are Winbond (continuous read capable) NAND chips mounted
> on TI platforms AM62 based which could make use of that new feature and
> expose the issue described above.

Applied to nand/next (except the spi patch).